Abstract
A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
C. Papachristou, S. Chiu, and H. Harmanani, “A Data Path Synthesis Method for Self-Testable Designs,” Proceedings of the 28th ACM/IEEE Design Automation Conference, June 1991, pp. 378–384.
L. Avra, “Allocation and Assignment in High Level Synthesis,” Proc. International Test Conference, Oct. 1991, pp. 463–472.
I.G. Harris and A. Orailoglu, “Microarchitectural Synthesis of VLSI Designs with High Test Concurrency,” Proceedings of the 31st ACM/IEEE Design Automation Conference, June 1994, pp. 206–211.
T.-C. Lee, N.K. Jha, and W.H. Wolf, “Behavioral Synthesis for Highly Testable Data Paths under the Non-Scan and Partial Scan Environments,” Proceedings of the 30th ACM/IEEE Design Automation Conference, June 1993, pp. 292–297.
S. Bhatia and N.K. Jha, “Behavioral Synthesis for Hierarchical Testability of Controller/Datapath Circuits with Conditional Branches,” Proceedings of the 1994 IEEE International Conference on Computer Design (ICCD-94), Oct. 1994, pp. 91–96.
S. Dey and M. Potkonjak, “Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs,” Proceedings of the 1994 International Test Conference, Oct. 1994, pp. 184–193.
S. Chiu and C.A. Papachristou, “ADesign forTestability Scheme with Applications to Data Path Synthesis,” Proceedings of the 28th ACM/IEEE Design Automation Conference, June 1991, pp. 271–277.
C.-H. Chen, T. Karnik, and D.G. Saab, “Structural and Behavioral Synthesis for Testability Techniques,” IEEE Transactions on CAD, Vol. 13, No.6, pp. 777–785, June 1994.
Z. Peng and K. Kuchcinski, “Automated Transformation of Algorithms into RTL Implementations,” IEEE Transactions on CAD, Vol. 13, pp. 150–165, Feb. 1994.
M. Abramovici, M. Breuer, and A. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1990.
K. Thearling and J. Abraham, “An Easily Computed Functional Level Testability Measure,” Proceedings of the 1989 International Test Conference, 1989, pp. 381–390.
V.D. Agrawal, “An Information Theoretic Approach to Digital Fault Testing,” IEEE Trans. on Computers, Vol. c-30, pp. 582–587, August 1981.
K.-T. Cheng and V.D. Agrawal, “An Entropy Measure for the Complexity of Multi-Output Boolean Functions,” Proc. 27th ACM/IEEE Design Automation Conf., June 1990, pp. 302–305.
X. Gu, K. Kuchcinski, and Z. Peng, “Testability Analysis and Improvement from VHDL Behavioral Specifications,” Proceedings of the Third European Design Automation Conference (EURO-DAC 94), Sept. 1994.
M.H. Gentil, D. Crestani, A. El Rhalibi, and C. Durante, “A New High Level Testability Measure: Description and Evaluation,” Proceedings of the 12th IEEE VLSI Test Symposium, April 1994, pp. 421–426.
J. Lee and J.H. Patel, “An Instruction Sequence Assembling Methodology for Testing Microprocessors,” Proceedings of the 1992 International Test Conference, Oct. 1992, pp. 49–58.
S. Davidson, private communication, July 1994.
H. Harmanani, C. Papachristou, S. Chiu, and M. Nourani, “SYNTEST: An Environment for System-Level Design for Test,” Proceedings of the First European Design Automation Conference (EURO-DAC 92), Sept. 1992, pp. 402–407.
Compass Design Automation, “User Manuals for COMPASS VLSI V8R4.4,” Compass Design Automation, Inc., 1993.
D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers, Boston, MA, 1992.
P. Vishakantaiah, T. Thomas, J. A. Abraham, and M. Abadir, “AMBIANT: Automatic Generation of Behavioral Modifications for Testability,” Proceedings of the 1993 IEEE International Conference on Computer Design (ICCD-93), Oct. 1993, pp. 63–66.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Carletta, J.E., Papachristou, C.A. Behavioral Testability Insertion for Datapath/Controller Circuits. Journal of Electronic Testing 11, 9–28 (1997). https://doi.org/10.1023/A:1008291616071
Issue Date:
DOI: https://doi.org/10.1023/A:1008291616071