A control and readout system for the BELLE silicon vertex detector

Abstract

A newly developed system for the control and readout of the BELLE silicon vertex detector (SVD) is described. The system is designed to meet the mechanical, electrical, and thermal requirements imposed by the BELLE detector. Its primary purpose is the amplification of analog signals from the VA1 front-end integrated circuits, which are used to read the silicon-strip detectors. It also provides a number of analog and digital functions related to the control and monitoring of the SVD. Much of the circuitry is implemented using programmable logic and analog devices, which allow a degree a flexibility in the design. In total, eight crates will be installed to read out the 81 920 strips from the three-layer double-sided silicon-strip detector array.

Introduction

The BELLE detector, which is currently under construction at KEK, has been designed for the study of the Kobayashi–Maskawa mechanism for CP violation and other topics in B physics [1]. An essential feature of BELLE is its ability to measure the expected asymmetry in the proper time distribution that occurs when one member of the neutral B-meson pair decays into a CP eigenstate. To this end, a silicon vertex detector (SVD) will be installed to make a precision measurement of the B decay vertices. In this paper, we describe the design and operation of the control and readout electronics (CORE) for the SVD.

A side view of the SVD in the BELLE detector (upper half) is shown in Fig. 1. The SVD comprises three layers of full ladders, which are composed of either two, three, or four DSSDs. A pair of 640-channel hybrid cards [2] is mounted at both ends of each full ladder. The total number of full ladders is 32 and the number of readout strips is 81 920.

The VA1¹ integrated circuit [3], [4] is employed as a front-end readout chip. Each VA1 includes preamplifiers, shapers, and track-and-hold circuits that capture the analog pulse-height information on 128 channels. The peaking time of the shaper circuits is set to $\text{2.5}\text{μ}$s so as to match the latency of the Level 1 trigger. Upon receipt of this trigger, the system is switched from track mode to hold mode and the stored analog information for each channel is sequentially routed via on-chip analog multiplexing (MUX) circuitry to a system of fast analog-to-digital converters (FADCs), which are remotely located in the experiment's electronics hut.

Functions of the CORE SVD readout system include:

• Remote control of the VA1 front end chips. This includes the setting of bias voltages and other analog levels that control the peaking time of the VA1's shaping amplifiers. The ability to adjust these levels remotely is particularly important in view of the possibility that the optimal set points may change over time as the chips are irradiated.

• Digital control of the VA1 front end chips. Various pulses and digital levels are used to control the data-acquisition sequence of the VA1s. The CORE system serves to condition, buffer, and distribute these signals to the VA1s.

• Analog buffering and amplification near the detector. Since the cable length between the detector and the electronics hut is more than 30 m, the CORE system incorporates differential gain/buffer stages to provide immunity to electromagnetic interference. To meet the readout speed requirements of the BELLE data acquisition system, the CORE system is capable of supporting MUX scan rates of up to 5 MHz. This allows a single FADC channel to scan all channels of a 640-channel hybrid in 128 μs.

• Monitoring of analog levels. The CORE system is capable of acquiring and digitizing a large number of analog levels that are used to verify that operating voltages of the SVD have been properly set.

Additional design constraints include the need to maintain low power consumption so as to minimize the temperature rise at the detector. This is necessary to prevent deformation of the mechanical support structure and to avoid increased leakage current in the DSSDs. Space constraints make it necessary to minimize the cable plant in the region near the DSSDs and inside the BELLE detector.

In the following section we describe the design concept of the CORE and present an overview of the readout system. Details of the CORE design are presented in Section 4.