Stochastic logical effort as a variation aware delay model to estimate timing yield

Highlights

• Proposed stochastic logical effort (SLE) delay model captures delay variations.

• One-time cell library characterization and linear SLE equations are presented.

• A Monte Carlo timing yield estimator based on SLE, called ISLE, is built.

• SLE and ISLE are tested in the existence of inter- and intra-die variations with correlations.

• ISLE speeds up standard Monte Carlo method about 180× on the average.

Abstract

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180× on the average for ISCAS’85 benchmark circuits and in the existence of both inter- and intra-die variations.

Introduction

Decreasing sizes of transistors result in manufacturing of digital integrated circuits (IC) to become much more difficult and prone to variations of parameters like transistor gate length, threshold voltage, etc. Performance (speed) variability due to the statistical parameter variations and environmental fluctuations has become more significant. IC designers need to estimate the timing yield and optimize their design accordingly until it reaches the desired yield before manufacturing. A survey [1] in 2011 by Solido Design Automation over 486 IC design professionals shows that two-thirds of designers and managers name variation-aware design as a top segment where technology advancement is needed.

In traditional VLSI design methodologies, designers prefer using Spice tool for detailed transistor level (TL) circuit simulations as a final verification before timing sign-off because of its accuracy. One would ideally like to perform a similar transistor-level, but statistical timing analysis for timing yield estimation. According to the above survey, more than half of the participant IC designers and managers want Spice simulators to be variation aware in the first place. Taiwan Semiconductor Manufacturing Company (TSMC) has already announced the insertion of transistor-level statistical timing analysis into its reference design flow in order to enhance timing accuracy [2]. There has been intense academic research on statistical timing analysis and timing yield estimation topics especially in the last decade [3], [4]. The researchers have to cope with hard problems like modeling inter- and intra-die variations with spatial correlations, accurate delay approximations without solving the actual non-linear and differential delay equations, propagation of the non-Gaussian random variables, etc. Previously negligible problems have become more and more important with the shrinking technology. Today, intra-die variations are at least as important as inter-die variations [5]. The combination of all these problems either increases the computational complexity of the solution or decreases the accuracy of the resultant timing yield estimate. Making too many assumptions to decrease complexity results in far-off estimates. The most accurate approach in statistical timing is the Monte Carlo (MC) method based on costly transistor level Spice simulations, which is the called golden method, however it is computationally too complex to be applicable.

The main contributions of this paper can be summarized as follows: a variation aware delay model, stochastic logical effort (SLE), is proposed to capture the tendency of a gate׳s delay with respect to the random device parameters. The characterization of a standard cell library to prepare it for SLE delay computation and efficient methods for the computation of SLE model parameters are presented. SLE is combined with a previously proposed importance sampling based timing yield estimation technique [6] to build a new estimator called ISLE. The theoretical error of the resultant ISLE estimator is derived in detail. The empirical tests over ISCAS’85 benchmark circuits considering both inter- and intra-die variations with spatial correlations show the accuracy of the SLE method. The results show that ISLE timing yield estimation is about 180 times faster on the average than the traditional methods with the same accuracy. ISLE is not meant to be a replacement of the less accurate but faster statistical static timing analysis methods, but instead a complementary method to be used as a final verification for the statistically critical paths in the circuit.

In Section 2, we present the variation aware gate delay model SLE. In Section 3, ISLE yield estimator is explained and a precise theoretical error analysis is given. Finally in Section 4, we present the experimental results and the computational cost.