Fig. 1. A HTP placement of six blocks.

Fig. 2. Three possible BBYs for different 10-pin nets.

Fig. 3. Two triangular coordinate systems adapting to the Y architecture.

Fig. 4. The typical case of bounding box of a net in the Y architecture.

Fig. 5. An example for the definitions of AR of BBY.

Fig. 6. Fit results for 10 000 instances of 30-pin nets for different AR definitions.

Fig. 7. Fit results by power function for 150 000 instances of 50-pin nets.

Fig. 8. Piecewise linear fit results for 150 000 instances of 50-pin nets.

Fig. 9. The wirelengths by different wirelength estimation techniques in the SA process.

Fig. 10. Best results of pwy33 (left) and pwy49 (right) with w₁=w₂=0.5 corresponding to the data in Table 9.

Average of the absolute value of the relative errors (AAE) of HPWL-Y wirelength to 3-SMT wirelength for 10 000 n-pin nets

Fit results of β and AR by power function for different net degree n.

The second and third rows give the parameters of power function. The row R² gives the R² values of fit. The row AAE gives the average of absolute value of relative errors of the fit values from the true values, over the corresponding 150 000 n-pin nets.

Piecewise linear fit results of β and AR for different net degree n

The row AAE gives the average of absolute value of relative errors of the fit values from the true values, over the 10 000 n-pin nets with the certain AR range. E(β) is the estimation value of β of the n-pin net.

Average of the absolute value of the relative errors (%) of wirelength by different techiniques

Average runtime (s) for nets of different degree

Benchmark information

Average of the absolute value of the relative errors (%) of wirelength by different techniques

3-SMT wirelength (WL), wirelength error, and runtime comparisons among placers using different techniques.

The column “3-SMT WL comp.” gives the 3-SMT WL reduction of HTP_APWLY to other two placers. The last column gives the runtime normalized by that of HTP_APWLY.

Best results with different weights