Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries
Introduction
Fault models are used extensively in the development of ASICs at various stages throughout the design process. Initially, the growth of fault modeling techniques was driven by the requirement to derive high quality tests for complex circuits [1]. In general, though, they are used during simulation for reproducing the abnormal circuit behavior caused by various defects. By definition, a defect is any physical imperfection that may exist within a circuit. Examples of defects include shorts or opens due to imperfections in the fabrication process or wear-out mechanisms such as electromigration. Since defects occur at the circuit level in digital ICs, the ideal simulation approach is using an analog simulator. However, since analog simulators have limited speed and capacity, we must resort to the use of digital simulators for studying defects occurring within the complex circuit designs of today. The main problem with this is that digital simulators are generally not capable of modeling defects, only faults. Formally, faults are defined as any type of abnormal circuit behavior, such as an incorrect logic level or increased signal delay. Thus, there is an intermediate, and often neglected, process whereby actual circuit defects must be mapped to appropriate fault models for use by digital simulators.
To fully justify the requirement for accurate fault models, it is necessary to define an error as it applies to digital circuits. An error is the unwanted effect of a fault that has propagated to some observable point in the circuit. By conducting fault simulation of typical IC defects, the test engineer can determine the expected number of defects excited to the error state, or fault coverage, of a set of test vectors. This information can then be used as a cost function by various algorithms to generate efficient sets of test vectors. Other applications of fault models also exist. For instance, in the design of fault secure circuits, fault models can be used to study the effects of defects on different design alternatives with respect to overhead and added benefit of fault security features [2], [3], [4], [5], [6], [7], [8], [9]. Furthermore, significant cost savings are realized by being able to objectively compare different fault secure designs early in the design process, without having to manufacture any hardware.
This paper begins with a discussion on various techniques commonly used for fault modeling, with specific emphasis on their limitations in terms of accuracy and realism. Then, an approach for deriving accurate fault models, based on analog defect simulation at the transistor level, will be outlined. Finally, a new software tool will be presented that provides an automated solution to the previously tedious task of conducting and analyzing analog defect simulations.
Section snippets
The stuck-at fault model
Prior to the late 1970s, fault modeling was a relatively simple process. At the time, it was widely accepted that typical IC defects behaved identically to cell inputs or outputs shorted directly to the ground or power supply rails. Thus, for testing and test pattern generation, defects could be injected into circuits or circuit simulations using relatively straightforward techniques. However, Wadsack published a paper in 1978 that demonstrated the weaknesses of the classical stuck-at fault
A CMOS transistor defect model
Studies have shown that typical IC defects have effects that can be accurately modeled at the transistor level as electrical shorts and open circuits. For instance, transistor defects that have been found to occur in CMOS technology are shown in Fig. 1 [29]. Three of these defects, the gate-drain short, gate-source short, and gate-channel short, represent the gate oxide shorts that have been shown to be dominant in all three phases of the device lifecycle [20]. The source-substrate and
Defect mapping and fault model generation tool
The defect to fault mapping and fault model generation is performed by a software tool referred to as D2F. It conducts the defect to fault translation procedure for an arbitrary component from an ASIC standard cell library and generates automatically a VITAL compliant VHDL fault model. The tool is implemented using the Tcl scripting language and the Tk Toolkit to provide an intuitive graphical user interface. The current version uses Cadence Spectre version 4.4.3 to conduct all analog
Sample results
Using the approaches described above, a defect to fault mapping was conducted for 81 standard cells from a cell library based on TSMC's 0.35 μm process. Following the defect to fault mapping, defect-injectable VITAL compliant VHDL models were generated for each of the 81 cells. These models are ready for immediate use in fault simulation of ASIC standard cell designs.
To demonstrate the results achieved from conducting the defect to fault mapping procedure, three cells from the 0.35 μm CMOS cell
Conclusions
This paper has presented an effective approach for defect to fault translation of ASIC standard cell libraries and the automatic generation of defect injectable fault models. The process begins with a detailed study of the physical defects that can occur within a given technology throughout its expected lifetime. Then, specific defect models are developed to enable study of the fault effects of the defects using analog simulation tools. Finally, individual cells within an ASIC library are
Donald B. Shaw received the B.Sc. (Electrical Engineering) and M.Sc. (Computer Engineering) degrees from the University of Manitoba, Winnipeg, MB, Canada, in 1994 and 1997, respectively. In 2001, he received the Ph.D. degree from the Royal Military College of Canada, conducting research in CMOS device/interconnect defects, fault modeling, and fault secure systems. He is currently employed as a video ASIC design engineer at Gennum Corporation in Burlington, Ontario.
References (48)
- et al.
Fault and error models for VLSI
Proc. IEEE
(1986) - et al.
Fault injection for dependability validation: a methodology and some applications
IEEE Trans. Software Eng.
(1990) - et al.
Xception: a technique for the experimental evaluation of dependability in modern computers
IEEE Trans. Software Eng.
(1998) - et al.
Simulated fault injection: a methodology to evaluate fault tolerant microprocessor architectures
IEEE Trans. Reliab.
(1990) - J. Coppens, Logical fault analysis of fault secure systems using VHDL. M. Eng. Thesis, Department of Electrical and...
- et al.
A fault injection technique for VHDL behavioral-level models
IEEE Des. Test Comput.
(1996) - et al.
Fault injection into VHDL models: the MEFISTO tool
- et al.
FERRARI: a flexible software-based fault and error injection system
IEEE Trans. Comput.
(1995) - et al.
A methodology for the rapid injection of transient hardware errors
IEEE Trans. Comput.
(1996) Fault modeling and logic simulation of CMOS and MOS integrated circuits
Bell System Tech. J.
(1978)
Physical faults in MOS circuits and their coverage by different fault models
IEE Proc.
Test pattern generation for realistic bridge fault models in CMOS ICs
Extraction and simulation of realistic CMOS faults using inductive fault analysis
Electrical characteristics and testing considerations for gate oxide shorts in CMOS ICs
Fault modeling
IEEE Des. Test Comput.
Test pattern generation for stuck-open faults using stuck-At test sets in CMOS combinational circuits
Limitations in predicting defect level based on stuck-at fault coverage
Current vs. logic testing of gate oxide short, floating Gate and bridging failures in CMOS
Fault modeling and defect level projections in digital ICs
Test considerations for gate oxide shorts in CMOS ICs
IEEE Des. Test Comput.
GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment
Logic testing of bridging faults in CMOS integrated circuits
IEEE Trans. Comput.
E-PROOFS: a CMOS bridging fault simulator
ASIC bridge fault modelling with neural network-based VHDL saboteurs
IEEE Trans. Comput.
Cited by (7)
Quantum circuit's reliability assessment with VHDL-based simulated fault injection
2010, Microelectronics ReliabilityAnalog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review
2024, IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsTest mode for FIR filter design using FPGA
2019, Journal of Advanced Research in Dynamical and Control SystemsAccurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level
2017, Proceedings - 2017 13th European Dependable Computing Conference, EDCC 2017Fault models of CMOS gates: An empirical study based on mutation analysis
2014, Proceedings - 2014 World Ubiquitous Science Congress: 2014 IEEE 12th International Conference on Dependable, Autonomic and Secure Computing, DASC 2014
Donald B. Shaw received the B.Sc. (Electrical Engineering) and M.Sc. (Computer Engineering) degrees from the University of Manitoba, Winnipeg, MB, Canada, in 1994 and 1997, respectively. In 2001, he received the Ph.D. degree from the Royal Military College of Canada, conducting research in CMOS device/interconnect defects, fault modeling, and fault secure systems. He is currently employed as a video ASIC design engineer at Gennum Corporation in Burlington, Ontario.
Dhamin Al-Khalili received the B.Sc. degree in 1966 and the M.Sc. and Ph.D. degrees in electrical engineering from the University of Manchester, UK, in 1970 and 1972, respectively. He joined the Ontario Centre for Microelectronics, OCM, in 1982, as a Senior Consultant, and then worked with the Canadian Semiconductor Design Association as a Research Director. Before joining OCM, he worked at the Winnipeg Microelectronics Center as a senior engineer and project leader. Prior to this he worked as Associate Professor and Chairman of School of Electrical Engineering at the University of Technology, Baghdad, Iraq. He also spent one year at Northern Telecom, Ottawa, as a Research Industrial Fellow. He is presently a Professor with the Department of Electrical and Computer Engineering at the Royal Military College of Canada, Adjunct Professor at Concordia University, Montreal, and Vice President of the Advanced Technology Education Consortium, Kingston. His research interests include VLSI architecture, low power electronics, testability analysis and design automation.
Côme N. Rozon received the M.Sc. degree (June 1977) in solid state physics from Sherbrooke University, Sherbrooke, Que., Canada, and the Ph.D. degree (August 1987) in Electrical Engineering from Queen's University, Kingston, Ont., Canada. From 1975 to 1983 he served as a Combat Systems Engineer in the Royal Canadian Navy and retired at the rank of Naval Lieutenant. In 1983 he joined the teaching staff of the Electrical & Computer Engineering Department at the Royal Military College of Canada, Kingston, Ont. He has worked as a consultant for Newbridge Networks and Nortel Networks. He has teaching commitments in electronics and digital design, and research interests in VLSI and Design For Testability applied to both binary and multi-valued logic systems. He held the position of Director of Computing Services at the Royal Military College of Canada and also served as Head of the Department of Electrical and Computer Engineering.