Efficient FPGA implementation of DWT and modified SPIHT for lossless image compression

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Abstract

In this paper, we present an implementation of the image compression technique set partitioning in hierarchical trees (SPIHT) in programmable hardware. The lifting based Discrete Wavelet Transform (DWT) architecture has been selected for exploiting the correlation among the image pixels. In addition, we provide a study on what storage elements are required for the wavelet coefficients. A modified SPIHT (Set Partitioning in Hierarchical Trees) algorithm is presented for encoding the wavelet coefficients. The modifications include a simplification of coefficient scanning process, use of a 1-D addressing method instead of the original 2-D arrangement for wavelet coefficients and a fixed memory allocation for the data lists instead of the dynamic allocation required in the original SPIHT. The proposed algorithm has been illustrated on both the 2-D Lena image and a 3-D MRI data set and is found to achieve appreciable compression with a high peak-signal-to-noise ratio (PSNR).

Introduction

Lossless image compression techniques find applications in fields such as medical imaging, preservation of artwork, remote sensing etc. [1]. In addition to being lossless, tools for compressing and decompressing medical images need to be implemented with high speed for accurate and timely diagnosis. Compressing an image set with multiple slices is very important in medical imaging as the most commonly used digital modalities, including Magnetic Resonance (MR), Computed Tomography (CT), Positron Emission Tomography (PET), and Single Photon Emission Computed Tomography (SPECT), generate multiple slices in a single examination [2], [3], [9]. One slice is normally a cross section of the body part. Multiple slices generated in this way are normally anatomically or physiologically correlated to each other. In other words, there are some image structural similarities between adjacent slices. Although it is possible to compress an image set slice by slice, more efficient compression can be achieved by exploring the correlation between slices. Methods to remove slice correlation for three-dimensional (3-D) compression include prediction methods and 3-D transformations.

Day-by-day Discrete Wavelet Transform (DWT) is becoming more and more popular for digital image compression. Biorthogonal (5, 3) and (9, 7) filters have been chosen to be the standard filters used in the JPEG2000 codec standard [1]. After DWT was introduced, several codec algorithms were proposed to compress the transform coefficients as much as possible. Among them, Embedded Zerotree Wavelet (EZW), Set Partitioning In Hierarchical Trees (SPIHT) and Embedded Bock Coding with Optimized Truncation (EBCOT) are the most famous ones [4]. While EBOCT has the best compression rate of all and is adopted by JPEG2000, it requires much more complex multi-layer coding procedures, multiple coding tables and arithmetic coding techniques. These make the hardware implementation of EBCOT codec more difficult and expensive. On the contrary, SPIHT, rooted from EZW, enjoys a much simpler coding procedure. If no entropy coding or arithmetic coding methods are incorporated, SPIHT does not require any table with slight loss in compression ratio. With SPIHT, the encoded bit stream can be divided into several successive sections of sub bit streams during the encoding process. With each additional data, the quality of the decoded image is better. This is very important for progressive transmission of digital images in application such as tele-medicine. Moreover, SPIHT can be easily used in fixed rate or variable rate transmission applications. Furthermore, SPIHT has about 0.6 dB peak-signal-to-noise-ratio (PSNR) gain over EZW and is very close to EBCOT in many circumstances [4]. With integer DWT, SPIHT can also be used in lossless image compression.

In the image processing applications, first the wavelet coefficients are stored in a 2-D array. Because searching for the descendants of a given coefficient has to be performed very frequently, it is necessary to design a dedicated circuitry to compute the coefficient addresses. This also consumes more number of clock cycles. Second, the three lists used in SPIHT algorithm store the coefficients coordinates. Transactions among the lists are required frequently. Third, linked lists are used as the data structure to store the coefficients. When there is a change to the list, insertion or deletion operations are necessary.

Based on the above observations, a modified SPIHT algorithm suitable for hardware implementation is presented in this paper. Through special arrangement of the coefficients, they can be stored in a 1-D memory array. As a result, the operation of searching for the descendants becomes very simple. Instead of using dynamic linked lists, fixed-size tables are used to complete the operations for the three lists. Transactions of the lists require no storage of the coordinates. Instead, only the flags stored in the tables are changed. Inspection of the content of the three lists becomes very convenient. The throughput is increased and the overall coding procedure is simplified.

This paper is organized as follows. Section 2 briefly introduces discrete wavelet transform and its implementation. A brief idea of SPIHT is given in Section 3. The modified SPIHT algorithm and design considerations are presented in Section 4. The differences are discussed in this section, too. Simulations and synthesis results are given in Section 5. The paper finally concludes in Section 6.

Section snippets

Discrete wavelet transform

As reported by Zervas et al. [7], there are three basic architectures for the two-dimensional DWT: level-by-level, line-based, and block-based architectures. In implementing the 2-D DWT, our proposed architecture is a hybrid of level-by-level and line-based architectures. Our goal is a small yet high performance system. We keep the hardware size small by using a single computing module iteratively for the higher level computations, and going back to external memory between levels. However,

Set Partitioning in Hierarchical Trees (SPIHT)

The SPIHT (Set Partitioning in Hierarchical Trees) algorithm, proposed by Said and Pearlman [8], is a highly refined version of the EZW algorithm. This technique has the advantages of:

  • Good image quality with a high PSNR.

  • Fast coding and decoding.

  • A fully progressive bit-stream.

  • Ability to code for an exact bit rate or PSNR.

The SPIHT algorithm is based on three concepts: (i) Ordered bitplane progressive transmission, (ii) Set partitioning sorting algorithm, (iii) Spatial orientation trees. A major

Design considerations and modifications

To get an efficient hardware implementation of the SPIHT compressor, we rely on a partitioned approach to wavelet transformed images [11]. Also, the sorting phase and the refinement phase are exchanged to save memory for status information. In the following, we present estimations for the memory requirements of these lists.

Considering a digital image with dyadic DWT decomposition, data arrangement used in the SPIHT algorithm is shown in Fig. 6. The arrow points to the descendants from a wavelet

Simulation results

The test images are 8 bpp gray scale images. Biorthogonal (5, 3) filter and 5-level DWT are used. The distortion measure is calculated byPSNR=10log10[2552/MSE]In the above, MSE denotes the mean-square-error between the original and the decoded image.

The decoded/reconstructed images while using the 2-D and 3-D SPIHT algorithm are respectively shown in Fig. 11, Fig. 12. The Lena image of size 512 × 512 was taken as input for evaluating the 2-D algorithm, and in the 3-D case, MRI scan of 128 slices of

Conclusions

An efficient image codec based on modified SPIHT and Lifting based DWT is presented in this paper. Use of the lifting structure allows implementation of symmetric extension without additional computations, giving lifting based architectures a significant advantage over convolutional filter bank-based architectures in terms of throughput and embedded memory consumption. The architecture given is easily scalable to accommodate additional lifting steps. The proposed algorithm employs a new

J. Jyotheswar graduated from Sri Venkateswara University, Tirupati, Andhra Pradesh in Electronics and Communications Engineering in the year 2003 and M.Tech. in Automation and Computer Vision from IIT, Kharagpur in the year 2006. He is currently working as Member (Research Staff) in Bharath Electronics Limited – Central Research Laboratory, Bangalore. His research interests are in design and hardware implementation of Digital Image processing algorithms.

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J. Jyotheswar graduated from Sri Venkateswara University, Tirupati, Andhra Pradesh in Electronics and Communications Engineering in the year 2003 and M.Tech. in Automation and Computer Vision from IIT, Kharagpur in the year 2006. He is currently working as Member (Research Staff) in Bharath Electronics Limited – Central Research Laboratory, Bangalore. His research interests are in design and hardware implementation of Digital Image processing algorithms.

Sudipta Mahapatra graduated in Electronics and Telecommunication Engineering from Sambalpur University in the year 1990. He obtained his M.Tech. and Ph.D. degrees in Computer Engineering from IIT, Kharagpur in the year 1992 and 1997, respectively. From April 1993 to September 2002 he was working in the Computer Science and Engineering department of National Institute of Technology, Rourkela, Orissa, India. He was in the Electronic Systems Design Group of Loughborough University, UK as a BOYSCAST Fellow of DST, Government of India, from March 1999 to March 2000. He is presently working as an Assistant Professor in the Electronics and Electrical Communication Engineering department of IIT, Kharagpur. His areas of research interest include lossless data compression hardware and parallel and distributed processing.

This work was supported in part by the SERC Fast Track Scheme of the Department of Science and Technology, Govt. of India.

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