Improved retention times in UTBOX nMOSFETs for 1T-DRAM applications

Abstract

This work aims to analyze the retention time as a limiting factor for the application of 1T-DRAM cell in future CMOS nodes. Two approaches are proposed in order to improve the retention time: by the source/drain structure engineering or by applying a pulsed back gate bias.

This work analyses the upgrade of the retention time by reducing the GIDL effect when the source/drain is underlapped with the gate.

A lower retention time is observed for shorter channel length even optimizing the constant back gate bias, but the underlap devices present better results. The Gate-Induced Drain Leakage (GIDL), its amplification by a narrower base of the bipolar transistor inherent in the MOS structure and the longer effective channel length are the responsible mechanisms for the degradation of the retention time in both holding-0 and reading-0.

The use of the pulsed back gate bias during write-1, as well as its variation, were analyzed. The pulsed bias case presents an improvement of 5% of the retention time and no difference was observed when the pulsed back gate level was varied.

Introduction

The single transistor dynamic random access memory (1T-DRAM), also called 1T-FBRAM by its working principles, has been developed since 1978, when the concept of changing the body potential by the injection/removal of charges was proposed for the first time in a Silicon-on-Sapphire substrate [1]. Recently, several methods to realize that concept were reported [2], [3], [4], [5], where the impact ionization combined with the parasitic BJT effect showed the best performance, improving the retention time and the current sense margin [6], [7], [8]. Although, these effects are normally considered as a parasitic one with reliability issues, in this case, it is necessary to enable the writing process. These reliability issues have already been studied in [5], [6].

Ultra-thin Buried Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) devices have originated from the buried oxide downscaling of SOI wafers. It has shown attractive characteristics in terms of short channel effects thanks to a reduction of the lateral electrostatic coupling between the channel and the drain [9], [10]. The main advantage of the thin BOX fully depleted SOI for the 1T-DRAM application is the better threshold voltage control by the back gate bias. This benefit can be further improved with a ground plane (GP) implantation which suppresses the depletion region under the buried oxide [11], [12]. However, to maintain the back gate bias reasonably low, the BOX thickness needs to be equal to or less than 10 nm [13]. Therefore, the UTBOX is a good candidate for 1T-DRAM applications, since the BJT effect is only activated when a high drain bias is applied which can be reduced by a higher back gate bias [10], [14], [15].

In this work, impact ionization combined with the BJT effect is considered for the write-1 operation. At high drain bias, the impact ionization (II) increases the hole concentration in the body, leading to a lower threshold voltage, increasing the drain current. This phenomenon is more pronounced in PDSOI. However, the main effect in FDSOI is the BJT one [16], [17]. In this case, the holes generated by the impact ionization act as the base current of the inherent BJT of the MOS structure which amplifies this current, resulting in a higher drain current and, therefore, intensifying the impact ionization. Then, with a positive feedback loop, the parasitic BJT is turned on, which is sensed during read-1 [4], [6].

In order to write the state-0, capacitive coupling was used for expelling the holes from the body through the junction, turning off the BJT effect, which is sensed as a lower drain current, i.e., the 0-state [4], [6].

In a conventional device, there is a lowly doped region between the source/drain and the channel. When this region is undoped, i.e., these regions have the same doping concentration and type of the channel, the structure is called underlap or extension-less devices. This technique minimizes the short channel effects due to its lower lateral electric field, leading to a more scalable structure, better analog performance and advantages in memory applications [18], [19], [20], [21], [22], [23].

One of the biggest issues is the retention time that scales together with the gate length of the cell [18], [24]. Besides, this parameter still needs to be further improved for achieving the 64 ms specification for standalone DRAM [25].

The back gate bias (V_B) has been shown to have an important impact on the memory read window [26], [27]. Higher V_B increases the memory window and the sense margin and lowers the required drain voltage V_D [15], [27], [28]. If V_B is too high, a high current is read for the state-0 and hence the sense margin is smaller. If V_B is too low, either not enough holes are generated during write-1 or the BJT effect does not turn on during the state-1 read [27], [28].

In order to overcome these issues, different source/drain engineering is used combined with UTBOX technology, showing an advantageous way of improving the device performance [19], [20] and also the pulsed back gate bias within its optimization allows to obtain a higher retention time.

The devices used in [29] presented a deeper isolation among different transistors of the same wafer, with their respective GP implantation, which allows the back gate biasing of only one transistor (memory cell) independently, reducing the disturbance on neighboring cells. In spite of the current memory cell array having only one back gate contact, it is possible to change the array layout in order to have an individual back gate contact using the structure shown in Ref. [29]. This approach can also be useful for a double gate device like MIGFET (Multiple Independent Gate Field Effect Transistor) as another degree of freedom for optimizing.

Therefore, firstly this paper studies the retention time scaling with the channel length in different source/drain junction engineering schemes and then, the pulsed back gate bias influence is analyzed as a way to improve the retention time.