Push the flash floating gate memories toward the future low energy application

Abstract

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell’s performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell’s performances in a memory array.

Introduction

The problem of energy saving has today a relevant importance, concerning in particular all portable devices as smartphones, tablet PC, smartcards and so on [1]. It is important to find a good tradeoff between the cell performances such as: consumed current, programming window and applied voltages. All these parameters can impact the design constraints of charge pumps and sense amplifiers as well as the effective chip area. The aim of this work is to show how it is possible to optimize the programming conditions and technological parameters, in order to reach the best floating gate cell performances, dependently on final application. In order to improve the features of portable products, particular attention is paid on energy consumption of flash cell in memory arrays. The research of new technologies and memory devices, has led to new solutions for the NOR embedded architectures: Phase Change Memories [2], Resistive RAM [3], and many others. Nevertheless, these very promising devices, destinated to substitute the flash Floating Gate (FG), show some drawbacks and prevent the technology switching, as for example data retention or high dispersion issues [4], [5], [6]. Waiting for solving these problems the floating gate remains a well known device based on full CMOS process [7], where it is possible to optimize some technological and electrical parameters in order to find the best trade-off between all these features.

To study the FG behavior, we developed a new method of measurement shown in [8]. With this kind of dynamic measurements, we quantify the drain current absorption during a Channel Hot Electron (CHE) programming operation. We evaluate the effects of gate pulse shape, performing some experiments with different ramp speeds and box pulse durations. The measurements of drain current allow to check the cell’s behavior and to calculate its energy consumption during the programming phase. The importance of the pulse shape is related to the presence of the drain current peak, when a box pulse is used [9]. This peak can disturb the circuits around the memory array [10]. Thus we show the important role of drain and bulk biases. It is possible to adjust the cell’s zone of work in order to decrease the energy consumption, but still keeping a good programming window. After these results concerning the programming signals optimization, we decided to look how to change some technological parameters to improve the cell performances. In particular the channel doping dose is important to control the charge injection.

To complete the study on energy consumption, we measured the role of all unselected cells in the memory array, which contributes with a bitline leakage to the current consumption. We investigate this effect and propose to change the lightly doped drain implantation energy as solution [11]. Particular attention is paid to the programming window that depends on the lightly doped drain (LDD) profile.