Capacitance and conductance characteristics of silicon nanocrystal metal–insulator–semiconductor devices
Introduction
Over the past decade metal–insulator–semiconductor (MIS) devices featuring self-organized silicon (Si) nanocrystals (NCs) embedded in the insulating layer (Si:NC-MIS devices) have received considerable attention, primarily in relation to non-volatile memory applications [1]. Essentially, the NCs act as charge storage centres whose charge state may be influenced by application of a DC bias voltage across the device. A change in the charge state of the NCs (i.e. addition or removal of electrons) is readily detected by capacitance–voltage (C–V) measurements, since a sustained change in the amount of charge stored in the NCs results in a flat band voltage (FBV) shift.
Typically C–V measurements are conducted on Si:NC-MIS devices with an asymmetric insulating layer. Namely, the distance between the NCs and the metal layer is significantly larger than the distance between the NCs and the semiconductor substrate. This sample geometry facilitates direct tunnelling of carriers between the semiconductor substrate and the NCs, whilst minimizing carrier exchange between the NCs and the metal layer. A consequence of restricting carrier transport between the metal and the NCs in this manner is that for moderate magnitudes of DC bias voltage, the total DC current through the device tends to be too small to significantly perturb the substrate from thermal equilibrium. That is, the electron and hole quasi-Fermi levels in the semiconductor substrate may be approximated as uniform throughout, and equal to the bulk Fermi level of the substrate.
Conversely, in cases where the insulating layer is relatively thin the DC current is potentially very large. This is a consequence of the increased probability that charge carriers will undergo direct tunnelling between the metal layer and the conduction band or valence band of the semiconductor substrate. If the insulating layer is sufficiently thin the DC current will be large enough to significantly influence carrier concentrations in the semiconductor substrate, which complicates the analysis of measured C–V curves considerably. Of course, the insulating layer thickness below which the DC current significantly affects C–V characteristics depends on the choice of dielectric and the density of defects therein, however in the case of the aluminium (Al)–silicon dioxide (SiO2)–Si system, where the SiO2 is thermally-grown and devoid of NCs, in theory the DC current tends to have a considerable bearing on C–V curves for insulator thicknesses less than 3 nm [2].
As in the case of MIS devices devoid of NCs, an increase in the DC current due to a reduction of insulating layer thickness (or an increase in the insulating layer defect density) may give rise to atypical physical phenomena in Si:NC-MIS devices. For example, Wu et al. [3] conducted C–V measurements on Si:NC-MIS devices featuring 13 nm SiO2 insulating layers fabricated by plasma-enhanced chemical vapour deposition (PECVD) and embedded with Si NCs 6 nm in diameter. Clear capacitance peaks were observed in the depletion and weak inversion regions of the C–V curves, which were attributed to carrier exchange between the semiconductor substrate and bound states arising from quantum confinement of carriers in the NCs.
The focus of this work is the experimental C–V and conductance–voltage (G–V) characteristics of Si:NC-MIS devices exhibiting DC currents high enough to significantly disrupt conditions of thermal equilibrium in the semiconductor substrate. MIS devices shall be classified as non-equilibrium devices if their DC current is sufficient to cause a deep depletion region (a region featuring falling equivalent parallel capacitance (C) and a linear 1/C2 vs. V characteristic, where V is the applied DC bias voltage) in their C–V curves. If this is not the case they shall be classified as equilibrium devices.
Section snippets
Fabrication and measurement
MIS devices featuring a layer of Si NCs embedded in SiO2 were fabricated on a (1 0 0) 1–10 Ω cm p-type crystalline Si substrate by radio frequency magnetron co-sputtering of a combined Si and SiO2 target, followed by high temperature annealing and device metallization. Device fabrication began with Radio Corporation of America (RCA) cleaning of the substrate [4], followed by a dip in 5% hydrofluoric acid (HF) to remove the native SiO2 layer. The substrate was then immediately loaded into the
Capacitance–voltage measurements
Fig. 3 depicts typical measured C–V curves of (a) a Si:NC-MIS device, and (b) a reference MIS device without NCs in the insulating layer.
In each case the specified voltage was applied to the top Al electrode with respect to the back Al contact. The depicted curves were measured one week after the high temperature anneal, and were generated by sweeping from positive to negative DC bias voltages at a sweep rate of approximately 23 mV/s. C–V curves were measured with small signal frequencies of 4
Conductance–voltage measurements
The G–V curves of the Si:NC-MIS device and the reference MIS device were measured simultaneously with the C–V curves reported in Section 3. Hence G–V curves were generated at room temperature for small signal frequencies of 4 kHz, 10 kHz, 100 kHz and 1 MHz, with a bias voltage sweep rate of approximately 23 mV/s. The measured G–V curves were corrected for series resistance (Rs) following determination of Rs by the method of Vogel et al. [18] for DC conductance much less than 1/Rs. Fig. 6 depicts the
Conclusions
MIS devices containing a layer of Si NCs in the insulating layer have been fabricated by RF magnetron sputtering. The C–V curves of these devices and reference MIS devices devoid of NCs are characterised by falling capacitance with increasing positive bias voltage in the region of strong inversion. This behaviour is consistent with depletion region widening with increasing positive bias voltage due to the electron current being semiconductor-limited. Observed frequency-dependent peaks in the
Acknowledgements
The authors thank Shujuan Huang and Yidan Huang for TEM analysis. One of the authors (C.F.) thanks Eun-Chel Cho, Young-Hyun Cho, Thipwan Fangsuwannarak and Chu-Wei Jiang for advice on sample preparation. This work was supported by the Global Climate and Energy Project (GCEP) of Stanford University as well as by the Australian Research Council (ARC) via its Centres of Excellence scheme.
References (23)
- et al.
Minority carrier MIS tunnel diodes and their application to electron- and photo-voltaic energy conversion-I theory
Solid-State Electron
(1974) - et al.
Capacitance–voltage study of SiO2/nanocrystalline silicon/SiO2 double-barrier structures
Thin Solid Films
(2003) Small-angle cleavage of semiconductors for transmission electron microscopy
Ultramicroscopy
(1991)- et al.
Current transport in metal–semiconductor barriers
Solid-State Electron
(1966) - et al.
Surface-state spectra from thick-oxide MOS tunnel junctions
Solid-State Electron
(1974) - et al.
Tunneling in MIS structures-I
Solid-State Electron
(1967) - et al.
Tunneling in MIS structures-II
Solid-State Electron
(1967) - et al.
Defects at the Si/SiO2 interface: their nature and behaviour in technological processes and stress
Nucl Instrum Methods Phys Res Sect A
(1996) - et al.
A silicon nanocrystals based memory
App Phys Lett
(1996) - et al.
Cleaning solutions based on hydrogen peroxide for use in silicon semiconductor technology
RCA Rev
(1970)
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