doi:10.1016/j.sse.2007.07.026 
Copyright © 2007 Elsevier Ltd All rights reserved.
Characterization of FD SOI devices and VCO’s on thin dielectric membranes under pressure
B. Olbrechtsa, 
, 
, B. Rueb, J. Suskic, D. Flandreb and J.-P. Raskina
aMicrowave (EMIC), Université catholique de Louvain, Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium
bMicroelectronics (DICE) Laboratories, Université catholique de Louvain, Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium
cMEMSFIELD, Rue Louis Guespin, 28, F-92140 Clamart, France
The review of this paper was arranged by Cor Claeys and Eddy Simoen.
Available online 6 September 2007.
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Abstract
In this paper, silicon-on-insulator MOSFETs and ring oscillators are, for the first time, fabricated and characterized on 1.5 μm-thick multilayered dielectric membranes, as a preliminary study for pressure sensing systems. Stresses were mechanically applied on these membranes, evolving drain current changes up to 5% in the devices characteristics, according to their channel type and orientation with respect to the stress, as well as resonance frequency shifts of −0.8% and +2.5% for the voltage controlled oscillators. Finite element simulations were performed, showing that the stresses are maximized at the center of the membrane anchors and pointing out the location for the devices to provide the best sensitivity. Internal membrane stresses are considered and discussed.
Keywords: Silicon-on-insulator MOSFETs; Devices on membrane; Pressure sensors; Ring oscillators; Bulk micromachining
Fig. 1. Schematic illustration of the process flow of the multilayered membrane with lying MOS device: (a) SOI thin film locally removed from oxidized starting SOI wafer on future membrane areas, (b) LPCVD silicon nitride film deposition and patterning according to the active zones, Si local wet thinning (c) LOCOS oxidation, (d) membrane’s nitride film deposition and RIE patterning, (e) gate oxidation and channel implantation, (f) source and drain implantation, (g) deposition of interconnect oxide, aluminum s-gun evaporation and passivation layer deposition, (h) wafer’s substrate grinding, metal layer evaporation and patterning, TMAH membrane release; the final system configuration.
Fig. 2. ANSYS simulation results for a 250 μm-side and 1 μm-thick membrane: (a) vertical deflection in μm (maximum of −1.5 μm at the center), (b) x-component of stress in MPa under 0.1 bar of pressure.
Fig. 3. x- and y-components of stress along the x-axis for 0.1 bar applied pressure.
Fig. 4. x-component of stress along the x-axis for various location inside the membrane material, from the top to the bottom fiber.
Fig. 5. Description of the measured structures and their devices configuration: (a) local view of 3 μm × 3 μm MOSFETs, the stress is mainly uniaxial, perpendicular to the drain current, (up device) or parallel to it (bottom device), (b) layout of a 250 μm side membrane with 20 × 20 μm devices located at its edges (anchors).
Fig. 6. Microphotograph of an oscillator pair at the border of a membrane. (a) left oscillator, the nMOS devices are parallel to the stress and pMOS are perpendicular, (b) right oscillator, the devices are inversely oriented.
Fig. 7. Output characteristics of perpendicularly oriented (gray lines) and parallel (black lines) intrinsic nMOSFETs at various gate biases: (a) ID − VD curves with (dashed lines) and without (solid lines) applied stress on the membrane, (b) the corresponding ID increase as a function of the drain voltage. L = 20 μm. W = 20 μm.
Fig. 8. Output characteristics of perpendicularly oriented (gray lines) and parallel (black lines) pMOSFETs at different gate biases: (a) ID − VD curves with (dashed lines) and without (solid lines) applied stress on the membrane, (b) the corresponding ID increase as a function of the drain voltage. L = 20 μm. W = 20 μm.
Fig. 9. Transfer characteristics of a SOI nMOSFET: Right axis – ID increase of perpendicularly oriented (gray lines) and parallel (black lines) transistor channel as a function of the gate voltage, in linear (VD = 50 mV, dashed lines) and saturation (VD = 2 V, solid lines) regimes when a mechanical stress is applied on the membrane. L = 20 μm. W = 20 μm. Left axis – the corresponding ID − VG characteristics of perpendicularly oriented device in linear regime.
Fig. 10. Transfer characteristics of a SOI pMOSFET: Right axis – ID increase of perpendicularly oriented (gray lines) and parallel (black lines) transistor channel as a function of the gate voltage, in linear (VD = −50 mV, dashed lines) and saturation (VD = −2 V, solid lines) regimes when a mechanical stress is applied on the membrane. L = 20 μm. W = 20 μm. Left axis – the corresponding ID − VG characteristics of perpendicularly oriented device in linear regime.
Fig. 11. VCO’s resonance frequency shift according to their orientation when a force is applied at the center of the membrane: (a) the channel of nMOS devices are parallel to the stress while the pMOS are perpendicular, (b) the channel of nMOS devices are perpendicular to the stress while the pMOS are parallel.
Table 1.
Thicknesses and stress values for the various films composing the membrane
Positive stress values mean tensile, while negative ones are compressive.
Table 3.
Extracted threshold voltage with and without applied stress and drain current increase under stress of an n-type MOSFET on membrane
L = 20 μm. W = 20 μm.
Table 4.
Extracted threshold voltage with and without applied stress and drain current increase under stress of a p-type MOSFET on membrane
L = 20 μm. W = 20 μm.
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