doi:10.1016/j.sse.2007.01.012 
Copyright © 2007 Elsevier Ltd All rights reserved.
Evaluation of triple-gate FinFETs with SiO2–HfO2–TiN gate stack under analog operation
M.A. Pavanelloa, b, 
, 
, J.A. Martinoa, b, E. Simoenc, R. Rooyackersc, N. Collaertc and C. Claeysc, d
aCentro Universitário da FEI, Av. Humberto de Alencar Castelo Branco, 3972, 09850-901, São Bernardo do Campo, Brazil
bLaboratório de Sistemas Integráveis, Universidade de São Paulo, Av. Prof. Luciano Gualberto, Trav. 3 n. 158, 05508-900 Sao Paulo, Brazil
cIMEC, Kapeldreef 75, B-3001 Leuven, Belgium
dE.E. Department, KU Leuven, Kasteelpark Arenberg 10, B-3001 Leuven, Belgium
The review of this paper was arranged by Raphaël Clerc, Olivier Faynot and Nelly Kernevez.
Available online 26 February 2007.
References and further reading may be available for this article. To view references and further reading you must
purchase this article.
Abstract
This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.
Keywords: FinFET; Analog operation; Triple-gate; Volume inversion; Intrinsic gain; Early voltage
Fig. 1. Schematic representation of a FinFET.
Fig. 2. Extracted (a) low field mobility (VDS = 0.1 V) and (b) Early voltage (VGT = 200 mV) for 10 μm long FinFETs as a function of the fin width.
Fig. 3. Extracted gm/IDS ratios for different channel lengths, WFin and halo implantation conditions at VDS = 0.8 V. Devices are halo doped with WFin = 120 nm except if indicated otherwise.
Fig. 4. Measured (a) IDS × VGF and (b) gm/IDS × IDS/(W/L) curves for L = 110 nm FinFETs at VDS = 0.65 V with a fin width of 120 nm and 370 nm.
Fig. 5. Tridimensional simulation of gm/IDS × IDS/(W/L) curves for an L = 400 nm FinFET at VDS = 0.8 V for different low field mobility values.
Fig. 6. Extracted Early voltage as a function of L for different WFin.
Fig. 7. Calculated intrinsic gain as a function of the channel length for FinFETs with WFin = 120 nm at VDS = 650 mV and VGT = 200 mV.
Fig. 8. Measured gm/IDS × IDS/(W/L) curves for L = 140 nm planar bulk and FinFETs (WFin = 120 nm and 370 nm) at VDS = 0.8 V.
Table 1.
Comparison between normalized maximum transconductance of FinFETs and bulk transistors with L = 140 nm at VDS = 0.1 V (for FinFETs W ≈ WFin + 2HFin)
Table 2.
Analog properties of L = 110 nm transistors obtained for the studied devices at gm/IDS = 5 V−1
Abstract
Purchase PDF (225 K)
E-mail Article
Add to my Quick Links
Cited By in Scopus (2)
Purchase PDF (606 K)
