doi:10.1016/j.sse.2005.08.001 
Copyright © 2005 Elsevier Ltd All rights reserved.
A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation
Michelly de Souzaa, 
, 
, Marcelo Antonio Pavanelloa, b, Benjamín Iñíguezc and Denis Flandred
aLaboratório de Sistemas Integráveis, Universidade de São Paulo, Av. Prof. Luciano Gualberto, trav. 3, n. 158, 05508-900, São Paulo, Brazil
bDepartamento de Engenharia Elétrica, Centro Universitário da FEI, Av. Humberto de Alencar Castelo Branco, 3972, 09850-901, São Bernardo do Campo, Brazil
cEscola Tècnica Superior d’Engenyeria, Universitat Rovira I Virgili, Tarragona, Spain
dLaboratoire de Microélectronique, Université Catholique de Louvain, Louvain-la-Neuve, Belgium
Received 4 May 2005;
revised 25 July 2005;
accepted 1 August 2005.
The review of this paper was arranged by Prof. A. Zaslavsky.
Available online 15 September 2005.
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Abstract
In this work a continuous analytical model for analog simulation of submicron asymmetrically doped silicon-on-insulator (SOI) nMOSFET using the graded-channel (GC) architecture, valid from weak to strong inversion regimes, is proposed. Analytical models accounting for mobility degradation due to the vertical field, channel length modulation, drain induced barrier lowering and velocity saturation effects have been included in the model formulation. Also the action of parasitic bipolar transistor intrinsic to the SOI MOSFET has been considered. The proposed model considers the highly doped part of the GC transistor acting as a ‘main’ transistor, whose drain voltage is modulated by the remaining part of the channel. Experimental results and two-dimensional simulated data were used to test the model, by comparing the drain current and some important characteristics for analog circuit design, such as the transconductance over the drain current ratio and output conductance, achieving a good agreement in both cases.
Keywords: Graded-channel SOI MOSFET; Device modeling; Analog simulation; Continuous model
Fig. 1. Cross-section of a graded-channel SOI nMOSFET.
Fig. 2. Comparison between simulated and modeled IDS versus VGF curves, obtained at VDS = 0.1 V (A) and 1.2 V (B). Lines: model. Symbols: simulated data.
Fig. 3. Simulated (symbols) and modeled (solid lines) IDS (VDS) and gD (VDS) curves for GC SOI MOSFETs obtained at VGT = 0 V (A) and −200 mV (B).
Fig. 4. Relation gm/IDS as a function of the normalized drain current for a GC transistor with L = 0.8 μm, LLD/L = 0.27 at VDS = 1.5 V obtained experimentally and through the proposed model.
Fig. 5. Measured (symbols) and modeled (lines) drain current and transconductance as a function of the gate voltage overdrive.
Fig. 6. Comparison between measured and modeled IDS versus VDS and gD versus VDS curves for 0.5 μm long GC SOI transistors, at VGT = 200 mV. Solid lines: model. Symbols: measurements.
Fig. 7. Comparison between measured (symbols) and modeled (lines) IDS versus VDS (A) and gD versus VDS (B) curves, obtained at different values of VGT for a 0.5 μm long GC SOI MOSFET with LLD/L = 0.29.
Table 1.
Extracted device parameters for GC SOI nMOSFET with L = 0.5 μm and LLD/L = 0.29
Table 2.
Comparison between modeled and measured maximum transconductance, for GC SOI nMOSFET with L = 0.5 μm, extracted at VDS = 0.1 V and 0.8 V
Table 3.
Experimental and modeled extracted Early voltages for GC SOI transistors with L = 0.5 μm biased at VGT = 200 mV
Table 4.
Experimental and modeled DC open-loop gain for GC SOI nMOSFET with L = 0.5 μm biased at VDS = 0.8 V and VGT = 200 mV
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