Elsevier

Solid-State Electronics

Volume 49, Issue 1, January 2005, Pages 109-116
Solid-State Electronics

SOI technology characterization using SOI-MOS capacitor

https://doi.org/10.1016/j.sse.2004.06.010Get rights and content

Abstract

In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found.

Introduction

Silicon-on-insulator (SOI) is emerging as a strong technology candidate for low-power, high-performance applications [1]. Integrated circuits fabricated on SOI substrates have been of increasing interest as the starting material has improved in quality, leading to highly promising circuit results. The present commercial SOI processes are mainly partially depleted (PD) SOI. However, thin film (fully depleted) SOI process provide a much better performance than PD SOI in circuits, due to the smaller body effect, the reduction of the kink effect, a better subthreshold swing and smaller short-channel effects.

The current vs. voltage (I–V) method in SOI-MOSFET has been used to determine silicon film and front oxide thicknesses [2] and front and back oxide charge densities [3]. The MOS capacitor is another structure used for process characterization. The high frequency capacitance vs. voltage (C–V) measurement is a well known and established method for extracting parameters in bulk technology [4] but in SOI technology, the use of C–V method is not straightforward [5].

Some researchers have studied SOI-MOS using the C–V method to determine the gate oxide, buried oxide and silicon film thicknesses, toxf, toxb and tSi, respectively [6], [7], [8], [9], [10] as well as to obtain the oxide charge density at the buried oxide/substrate interface (Qox3) [11], at the gate oxide/silicon film interface (Qox1) [12], at the silicon film/buried oxide interface (Qox2) [13] and effective silicon film doping concentration (Ndf) [13].

In this work, a set of simple methods is presented for determining eight parameters of SOI technology through SOI-MOS capacitor.

Section snippets

SOI-MOS capacitor with two terminals

Fig. 1 shows P-type SOI-MOS capacitor structure with two terminals. The equivalent association of capacitors model is also presented, including the substrate capacitance (CSUB) and neglecting the interface trap capacitance.

When a high negative voltage is applied in the front gate (VGF), the substrate interface is accumulated and the substrate capacitance (CSUB) becomes very high. Then, the total capacitance, that is the series association of the silicon film capacitances (CSi), CSUB, the front

SOI-MOS capacitor with three terminals

There are two kinds of SOI-MOS capacitors with three terminals. The accumulation one, similar to accumulation mode SOI-MOSFET, where the silicon film contact region is the same type (N or P) as the silicon film below the gate. The inversion one, similar to inversion mode SOI-MOSFET, where the silicon film contact region and the silicon film below the gate are different as shown in Fig. 3. The front channel capacitance (CFC), between the front gate and the silicon film is indicated, which is the

Numerical simulations

Numerical bidimensional simulations MEDICI [18] were carried out to test the proposed methods.

SOI-MOS with two terminals

Measurements of the high frequency capacitance vs. voltage were realized in capacitors fabricated in 0.5 μm SOI CMOS technology done at IMEC/Belgium using a SIMOX wafers with A = 2.5 × 10−3 cm2, toxf = 15 nm, toxb = 400 nm, tSi = 70 nm, Naf = 1 × 1017 cm−3 and N+ poly gate. These curves were performed in the LCR HP4280 at 1 MHz.

Fig. 2 shows the experimental C–V curves. Applying the proposed methods considering Qox1/q = 1 × 1010 cm−2 and Qox2/q = 5 × 1010 cm−2, the average results are Nab = 3.2 × 1015 cm−3, toxb = 394 nm

Conclusions

In this work the capacitance vs. voltage curves of SOI-MOS capacitors with two and three terminals were analyzed.

Simple methods to determine the substrate doping concentration, the substrate interface charge density and the buried oxide thickness using high frequency capacitance vs. voltage curve of SOI-MOS capacitors with two terminals were proposed. Simple methods to determine the front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back

Acknowledgments

The authors would like to thank IMEC and UCL for supplying the devices and Marcelo A. Pavanello and Mauricio M. Oka for stimulating discussing.

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