The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM
Introduction
GaN, as a member of 3rd generation semiconductors, has a significant potential in high power and high speed applications due to its wide energy band gap of 3.4eV, high critical breakdown field of 3.3 MV/cm and high saturation velocity of 2.5 × 107 cm/s [1,2]. Recently, GaN-based power devices, especially high electron mobility transistors (HEMTs) on silicon substrate, are widely explored and trigger commercial interest because of their relatively simple manufacturing process and low-cost substrate [[3], [4], [5], [6]]. However, the heteroepitaxy GaN on silicon suffers from challenges in improving the performance and reliability of AlGaN/GaN HEMTs, like current collapse and premature breakdown. A vertical MOSFET structure is widely adapted for Si-based power devices, enabling a higher current density within a small chip area and reducing parasitic effects [7,8]. Despite the relatively complicated fabrication process, vertical GaN power devices make it easier to realize enhancement mode operation and avalanche breakdown to achieve the best figure of merit (FOM) [9,10]. A GaN-based trench gate MOSFET (TG-MOSFET), recently reported by TOYODA GOSEI has set a record for normally-off GaN power devices [11,12]. However, the reported values are still far away from the theoretical limit for GaN devices because of premature breakdown in the gate dielectric at the trench corners, which is a symptomatic problem for TG-MOSFETs. Thus, it is of great importance to optimize the GaN TG-MOSFET design to prevent the electric field crowding at the trench corners. As reported in Refs. [13,14], the floating island (FLI) concept was proposed for silicon TG-MOSFETs in order to break the theoretical silicon limit for Si-based power devices by reducing the peak field in the drift region and realizing a lower specific on-resistance. This idea has also been applied to SiC TG-MOSFETs, achieving the same effect of suppressing the high electric field in the gate oxide and thus enhancing the breakdown voltage [15,16]. However, the effect of FLI for GaN TG-MOSFETs has not been investigated yet and the role of various device parameters for GaN TG-MOSFETs with FLI to guide the device optimization has not been reported. Additionally, the FLI concept is relatively easy to realize in case of GaN by a multiple epitaxial overgrowth process compared to a more complex superjunction technology, Because superjunction should be made by several times of alternate epitaxial overgrowth and ion implantation process, and good charge balance between P and N columns cannot be maintained even if fabricatable [17].
A novel GaN TG-MOSFET with FLI (FLI TG-MOSFET) is proposed in this paper and the main focus is to examine effect of the FLI by two-dimensional (2D) device simulations using the Sentaurus Device Simulator that how the existence of FLI contributes to shield the gate oxide at the bottom of the gate trench from the high electric field during the blocking state, meanwhile improving the Baliga's figure of merit (BFOM). Moreover, the effect of doping concentration, length and position of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is investigated, and an optimized structure is put forward. Regarding to BFOM, the FLI TG-MOSFET shows better performance than the best reported results for normally-off GaN-based power devices, closer to theoretical limit for GaN.
Section snippets
Device structure and models
Firstly, the reported experimental results of a conventional GaN TG-MOSFET in Ref. [11] have been investigated As a benchmark test for our simulations. Fig. 1(a) illustrates the structure of the conventional GaN TG-MOSFET. The structure parameters used in the simulation are based on the reported values, as indicated in Table 1. In the following, we briefly summarize relevant models used in simulations. The mobility models include concentration dependent mobility with high field saturation
Results and discussions
In order to understand the influence of FLI geometry parameters on device performance, simulations with various thickness (tp), distance to P-Well (Dp), length (Lp) and doping concentration (Np) (Fig. 1(b)) have been performed.
Conclusions
A novel GaN trench gate (TG) MOSFET with floating islands (FLI) is proposed and compared to conventional GaN TG-MOSFETs reported by TOYODA GOSEI as benchmark, using the Sentaurus device simulator. Based on the device structure, the electric field peak at the bottom corner of the gate trench can be reduced by inserting P-type floating islands (FLI) in the drift region and the avalanche breakdown voltage of the device is significantly improved. The influence of the FLI geometry parameters on the
Acknowledgements
This work was supported by the National Natural Science Foundation of China (grant no. 11175229) and the Joint Doctoral Promotion Programme (DPP) between Fraunhofer and CAS.
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