Elsevier

Organic Electronics

Volume 15, Issue 12, December 2014, Pages 3609-3614
Organic Electronics

Sub-100 nm ALD-assisted nanoimprint lithography for realizing vertical organic transistors with high ON/OFF ratio and high output current

https://doi.org/10.1016/j.orgel.2014.10.008Get rights and content

Highlights

  • Atomic-layer-deposited AlOx coverage assists the sub-100-nm nanoimprint.

  • The ALD-assisted NIL successfully produces organic transistor with ordered vertical-nano-channels.

  • The ALD-assisted imprint transistor delivers high ON/OFF ratio and large output current density at low operation voltage.

Abstract

We introduced a conformal atomic-layer-deposited aluminum oxide layer to cover the imprint mold to reduce the feature size and to strengthen the mold durability. A nano-hole array pattern with diameter down to 85 nm was successfully transferred to sample substrate to fabricate a vertical organic transistor. The Imprint vertical organic transistor exhibited high output current density as 4.35 cm2/V s and high ON/OFF current ratio as 11,000 at a low operation voltage as 1.5 V.

Introduction

Compared to the traditional amorphous-silicon thin film transistors (a-Si TFTs), the solution-processed organic transistors are promising for the development of low-cost and large-area electronic devices on flexible substrates [1]. Since the high operation voltage caused by long channel length of the conventional transistor would bring about high power consumption, the organic transistors with vertical channels were introduced to lower down the operation voltage [2]. In the previous work, we reported that a vertical-channel solution-processed organic transistor, named space-charge-limited transistor (SCLT), showed promising transistor characteristics such as higher output current (>10 mA/cm2) at 2 V operation voltage [3], [4]. As shown in Fig. 1(a), the carriers are injected into the vertical organic semiconductor channel by an emitter, passing through the holes on the base, and finally being collected by the collector. Base electrode controls the potential profile in vertical channel to turn on or turn off the transistor. The colloidal lithography was then employed to make the base electrode in SCLT with a hope of its potential mass production. However, colloidal lithography used in our previous work might not be compatible with existing commercialized process tools, and even worse the inevitable random accumulation of nanospheres during the process could incur large holes on the base electrode of SCLT, causing leakage current and made it difficult to have uniform leakage control [3]. A solution to completely removing such accumulation was to use nano-imprint lithography (NIL). The SCLT made by using NIL exhibited an ON current of 0.35 mA/cm2 and an ON/OFF current ratio of around 3000 at 1.8 V [5]. It was noted that the hole diameter of base electrode was the key parameter in determining the ON/OFF current ratio of an SCLT [6], [7]. Base control ability was improved with reduced hole diameter and hence the off state current was decreased. Additionally, it is apparent that the larger the area of holes array pattern, the more SCLTs can be accommodated, which benefits the mass production. However, the sub-100 nm resolution NIL usually requires e-beam lithography to generate the imprint mold, which is expensive and low-throughput especially when a large area is to be patterned. Interference lithography (IL) can fabricate large-area, periodic nano-holes array patterns in much shorter time [8]. The period of IL is governed by Λ = λ/2sin θ, where Λ is the pattern period, λ the wavelength of light source, and θ the incident angle of light. Therefore, the inherent linewidth is limited; for example, it will not be smaller than 91 nm if a light source in 364 nm wavelength is used. To overcome this limit, in this work we will introduce a novel method which combines low-temperature atomic layer deposition (ALD) and IL to fabricate a sub-100 nm resolution hole-array photoresist (PR) pattern NIL mold. The PR structure coated with aluminum-oxide layer can be directly used as an imprint mold. By employing this method, the ON current of SCLT can increase to 4.35 mA/cm2, 10 times more than before, and the ON/OFF current ratio can have a 300% increase to be greater than 104.

Section snippets

Experimental

The process steps to fabricate stamp and to produce Imprint SCLT are illustrated in Fig. 1(b) and (c), respectively.

(1) Stamp fabrication: Firstly, a mold on silicon substrate was prepared. The 175-nm-thick antireflection coating (ARC, from Nissan Chemical XHRiC-11, baked at 175 °C for 1 min) and the 200-nm-thick photoresist (ULTRA-i™ 123, ©Rohm and Haas Electric Materials, soft baked at 90 °C for 90 s) were coated on the silicon substrate. ARC was used to suppress the light reflection from bottom

ALD-assisted imprint process

Since the thickness of aluminum layer in an SCLT was around 40 nm, the sidewall thickness of hole-array pattern should be greater than 50 nm to accommodate the tolerance needed for wet etching the aluminum layer. If the diameter of hole was set to be 120 nm, the period of IL pattern would be 170 nm, which was beyond the current capability of our IL system. As described previously the smaller the diameter, the higher ON/OFF current ratio and the higher ON current of SCLT would be expected. The

Conclusion

We demonstrated high performance vertical channel organic transistor by using ALD-assisted nano-imprint technology. A conformal aluminum oxide layer grown by atomic layer deposition covered the imprint mold to reduce the feature diameter from 180 nm to 85 nm. With the reduced feature size, imprinted nano-hole array was used to reduce the diameter of vertical channel. The reduction of channel diameter could significantly enhance base electrode control over the vertical channel and hence greatly

Acknowledgement

The authors like to thank Mr. Chia-Ho Lin, Mr. Yung-Tai Sun, and Miss Huei-Tzu Chin for their kind support to perform part of the nanoimprint process. The authors are also gratitude to Ministry of Science and Technology, Taiwan for her national nano project (103-2120-M-009-003-CC1) and to National Taiwan University for her international collaboration project (NTU-ICRP-103R7558).

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1

Yung Hsu and Xiang Fang contribute equally to this work.

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