Adhesion study of low-k/Si system using 4-point bending and nanoscratch test

doi:10.1016/j.mseb.2005.03.030

Materials Science and Engineering: B

Volume 121, Issue 3, 15 August 2005, Pages 193-198

https://doi.org/10.1016/j.mseb.2005.03.030 Get rights and content

Abstract

Chemical vapour deposited (CVD) low-k films using tri-methyl-silane (3MS) and tetra-methyl cyclo-tetra-siloxanes (TMCTS) precursors were studied. A 4-point bend test (4PBT) was performed to assess the adhesion property of the low-k films to Si substrates and the results were compared with that of simpler method, nanoscratch test (NST), as a quality control tool despite its drawbacks. Adhesion energy, G_c, of the low-k/Si interface as measured by 4PBT and critical scratch load, P_c, as obtained by NST display a linear relationship with hardness and modulus of the low-k film. The lowering of G_c as the hardness of the film decreases can be explained by the effects of the C introduction into the Si single bond O networks found in these films. Lower carbon content for higher hardness films is thought to cause them to be more “silica-like”, and thus, exhibit better adhesion with the Si substrate. Two failure modes were observed for specimens under 4PBT. On one hand, films with low hardness (<5 GPa) exhibit low G_c (<10 J/m²) with an adhesive separation of low-k from the Si substrate. On the other hand, films of high hardness (>5 GPa) display interfacial energies in excess of 10 J/m² with delamination of epoxy from the Si substrate, thus, indicating excellent adhesion between the low-k films and Si substrate. For the low hardness films, good correlation exists between P_c and G_c. However, the two data points of the high hardness films that gave the two highest P_c and G_c values do not lie on the correlation line drawn for the low hardness film data points due to different factors governing the failure in both tests and a change in the 4PBT failure mechanism.

Introduction

Ultra large scale integration in microelectronics circuits has necessitated the use of newer thin films in wafer fabrication. Examples are films with dielectric constants (k) lower than SiO₂, and those with electrical resistivity lower than Al [1].

Reduction in the dielectric constant can be brought about by introducing pores into the films or by reducing the polarization [1]. However, both methods result in new structures which have inferior mechanical strength compared to silica. Integration of such new films into already established fabrication procedures and film stack designs could cause incompatibility problems. Adhesion between adjacent films may not be adequate and, in some cases, excessive inter-diffusion could create problems. This paper addresses the issue of film adhesion.

Several techniques are employed to assess the adhesion of thin films to substrates. Of these, the nanoscratch test [2], [3], the peel test [4] and the modified edge lift-off method [5] are easy to perform and give empirical results that are adequate for the purpose of qualitative comparison. A deficiency in these tests is that during the process of decohesion, the residual stress in the film relaxes and contributes to the driving force for further decohesion. Thus, the results may not give an accurate estimate of the interface quality. A 4-point bend test (4PBT), which was developed more recent than other adhesion methods, is more quantitative and seems to eliminate the deficiency of the other tests [6]. The specimen in this test is sandwiched between two massive elastic substrates so that the constraint is adequate to prevent stress relaxation in the film during decohesion. However, 4PBT is time consuming, tedious and requires careful sample preparation. Therefore, if a good correlation could be proved between 4PBT and the simpler tests, then one of the simpler tests may be preferred as a quality control tool despite its drawbacks. In this work, the 4PBT and the nanoscratch test (NST) are done and the results are compared.

A set of new low-k films on Si wafer were chosen for this study to compare the 4PBT with the NST. These films are deposited from two precursors, tetra-methyl-silane (3MS) and tetra-methyl cyclo-tetra-siloxanes (TMCTS) by a proprietary process using plasma-enhanced chemical vapour deposition. The films generated are essentially a form of modified SiO₂ and their hardness could be varied to some extent by manipulating the deposition conditions. These films have potential for commercial applications, and thus, were chosen.

Section snippets

Experimental procedures

A series of low-k films were deposited on 200 mm, p-type (1 0 0) Si wafers by plasma-enhanced chemical vapour deposition (PECVD) with TMCTS and 3MS as precursors using Novellus Sequel™ and Applied Materials™ equipments, respectively. The nominal thickness of the low-k films was approximately 1.5 μm. By controlling the process parameters, films of different hardness were obtained from both precursors. Details of the deposition process optimization were published elsewhere [7], [8], and hence, are

Results

Three typical load versus displacement curves obtained from 4PBT are shown in Fig. 3. The curves are for different film hardness values: a low hardness film, a medium hardness film and a high hardness film. Initially, the load increases linearly as the specimen deforms elastically. At some point, the load decreases abruptly, which signifies the point at which the vertical crack initiated by the notch begins to propagate through the Si. When it reaches an interface, it might be either deflected

Discussion

Crack penetration across an interface into the adjacent material is thought to occur when the interface fracture toughness exceeds about one quarter of that of the material across the interface [13]. Thus, crack propagation across the Lk–Si interface was never observed as the toughness of Si is much higher. For low-k films of hardness <5 GPa, both the toughness of the Lk–Si interface and that of the film are low. Hence, the crack is occasionally deflected back towards the epoxy layer causing the

Conclusions

Increasing the hardness of low-k films produced by plasma-enhanced chemical vapour deposition from the two precursors increases their dielectric constant, elastic modulus and fracture toughness. As determined by 4PBT, the adhesion energy, G_c, of the low-k/Si stacks increase with the film's hardness. The same trend was observed for the nanoscratch test whereby the critical load, P_c, of the low-k/Si stacks increase with the film's hardness. One possible explanation would be because of higher

References (13)

M. Uhlig et al.
J. Microe. Eng.
(2000)
L.Y. Huang et al.
Diamond Relat. Mater.
(2002)
R.H. Dauskardt et al.
Eng. Fract. Mech.
(1998)
A.A. Volinsky et al.
Thin Solid Films
(2003)
M.Y. He et al.
Int. J. Sol. Struct.
(1994)
K. Maex et al.
J. Appl. Phys.
(2003)
F. Erickson et al.
Mater. Sci. Eng. A
(1988)
J.A. Kerr, in: D.R. Lide (Ed.), CRC Handbook of Chemistry and Physics 1999–2000. A Ready Reference Book of Chemical and...

There are more references available in the full text version of this article.

Cited by (41)

A study on the interfacial adhesion energy between capping layer and dielectric for cu interconnects
2021, Microelectronics Reliability
Citation Excerpt :
Therefore, it can be inferred that formation of SiO bonding at the interface enhances the adhesion. This shows a similar result to the study that SiO bond in low-k/Si interface showed improved interfacial adhesion energy because SiO bond (799.6 kJ/mol) had higher bonding energy than SiC bond (451.5 kJ/mol) [17,18]. A similar result of forming a SiOxNy film of −6 nm thick at the SiN/low-k (bottom/upper) interface is observed in Fig. 4 (a).
Recently, Cu interconnect and low-k materials have been applied to reduce the interconnect resistive-capacitive delay issue. However, as the process node size is reduced to a few nanometers, high leakage currents appear through the dielectric under high electric fields. Therefore, issues of Cu diffusion at the interface between the dielectric and the capping layer have been reported. This study investigated interfacial adhesion energy change at the film level between dielectric (low-k, tetraethyl orthosilicate (TEOS)) and capping layer (SiCN, SiN) taking into account the correlation between interfacial adhesion energy and interconnect reliability. In the capping layer/low-k interface, when low-k is applied to the top layer, it shows high interfacial adhesion energy (> 34.31 ± 3.49 J/m²) due to the presence of an O-rich thin layer. But when low-k is applied to the bottom layer, due to the SiC bond, it shows low interfacial adhesion energy (< 5.60 ± 2.46 J/m²). The interface between TEOS and SiN has high interfacial adhesion energy (> 32.54 ± 1.97 J/m²) regardless of the stacking order and CMP process. It clearly shows that low-k dielectrics will affect the deterioration of the interfacial adhesion energy and O-rich layer will greatly improve the interfacial adhesion energy in dielectric/capping layers.
Improved adhesion of carbon nitride coatings on steel substrates using metal HiPIMS pretreatments
2016, Surface and Coatings Technology
Citation Excerpt :
The scratch length was set to 5 μm and the normal load was increased with a rate of 25 μN/s. The critical loads, Lc1, Lc2, and Lc3, and the corresponding critical penetration depths, hc1 and hc2, at which delamination events occurred, were extracted from the curves of penetration depth (normal displacement of tip) versus lateral force [31,32]. Cross-sectional scanning electron microscopy (SEM, LEO 1550 Gemini) was used to determine the thickness of the CNx coatings.
We investigate the effect of low-temperature metal pretreatments in order to improve the adhesion of CN_x coatings on steel substrates, which is crucial for tribological applications. The substrate pretreatments were conducted using five different metal targets: Ti, Zr, Al, Cr, and W, operated in high power impulse magnetron sputtering mode, known to produce significant ionization of the sputtered material flux. The CN_x adhesion, as assessed by Rockwell C tests, did not improve upon Ti and Zr pretreatments. This is primarily ascribed to the fact that no interlayer was formed owing to severe re-sputtering due to high fluxes of doubly-ionized metal species in the plasma. A slight improvement in adhesion was observed in the case an Al pretreatment was carried out, while the best results were obtained using Cr and W. Here, 30-s-long pretreatments were sufficient to clean the steel surface and form a metallic interlayer between substrate and coating. Transmission electron microscopy in combination with energy dispersive X-ray spectroscopy revealed that Al, Cr, and W created intermixing zones at the interlayer/substrate and the interlayer/CN_x interfaces. The steel surfaces, pretreated using Cr or W, showed the highest work of adhesion with W^Cr_adh = 1.77 J/m² and W^W_adh = 1.66 J/m², respectively.
Prediction of interfacial adhesion strength of nanoscale Al/TiN films passed through patterned BEOL interconnects
2015, Materials Science in Semiconductor Processing
Citation Excerpt :
Moreover, predictions of the crack arrest length have been discussed from pre-crack and consistent energy viewpoint [7]. Given that highly scaled interconnects are composed of low-k films and Al metals have been introduced into advanced integrated circuits (ICs), assessment of the adhesion property low-k films by using 4-PBT has become significant [8]. A critical energy release rate (G) of approximately 5.3 J/m2 for interfacial adhesion of Ta/low-k (Black Diamond, k-value of 2.9), which is another barrier system, is ensured [9].
The patterned layout arrangement of back-end of line (BEOL) is an important factor among reliability issues of advanced interconnects technology. BEOL determines the likelihood of interfacial fracture when adhesion between dielectric materials and conductive metals becomes poor, especially when ultra low-k dielectric is introduced into the process of semiconductor devices. Interfacial delamination of dissimilar thin films comprising multi-level interconnects increases under external loading or thermal cycling stress during device manufacturing. An Al/TiN coating underneath an ordinary pattern of BEOL interconnects is selected in this research to estimate adhesive energy by using interfacial fracture theory based on finite element analysis. By adopting the framework of four-point bending test, the proposed simulated approach was validated before comparison of the adhesion of Al/TiN stacked coatings with experimental data. Analysis indicate that increasing dielectric thickness between interfaces of Al/TiN films and Al metal line patterns from 100 nm to 600 nm induces fracture growth with crack lengths exceeding 3.5 mm. In addition, the foregoing driving force of fracture could be achieved because of Young’s modulus of dielectrics, which are larger than 70 GPa.
Investigation of interconnect design on interfacial cracking energy of Al/TiN barriers under a flexural load
2013, Thin Solid Films
The integration of thin film technology into the fabrication of semiconductor transistors has given rise to significant challenges in the design of multi-level back-end-of-line interconnects. The interfacial adhesion between Al metal and TiN barrier is one of the major factors that affect interconnect reliability. Analyzing the effect of the interconnect structures of Al/TiN barriers on interfacial cracking energy under flexural loading is an interesting research direction. This work proposes a robust estimation of interfacial cracks by simulation-based methods to satisfy the mechanical design requirements for multi-level interconnect systems. A constant bending moment can be generated with the framework of the four-point bending test (4-PBT). A 4-PBT simulation model can be used in finite element analysis, combined with the J-integral method and the modified virtual crack closure technique, to accurately predict the interfacial fracture energy of Al/TiN films. Preliminary results indicate a considerable increase in energy release rate. Energy is released as a crack along the interface of the Al/TiN films passes through the region above the parallel metal lines of patterned interconnects, especially for a Cu/SiLK material system. The results also show that dielectrics can serve as stress buffer layers that inhibit crack growth.
Patterned film effects on the adhesion of Al/TiN barrier using fracture-energy based finite element analysis
2013, Surface and Coatings Technology
Citation Excerpt :
On the other hand, a small critical energy release rate (G) is usually obtained in advanced integrated circuits (ICs) with an introduction of highly scaled Cu/low-k interconnects, such as approximately 5.3 J/m2 for Ta/low-k interface (Black Diamond, k-value of ~ 2.9) [12]. Therefore, the determination of the sensitivity of 4-PBT in fracture energy measurement has become significantly important [13]. Specimen preparation in 4-PBT is extremely complicated and time consuming.
The interfacial adhesion of thin films between Al metal and TiN barrier is one of the major concerns dominating the mechanical reliability of semiconductor devices. The measured accuracy of cracking energy for stacked films with a nanoscale order is arduous to preserve because of the uncertainty in specimen preparations and instrumental operations. Consequently, the present research proposes a robust estimation of interfacial cracks using simulation-based methodologies to meet the requirement for mechanical designs in multi-level interconnected systems of electronic devices. According to the framework of the four-point bending test (4-PBT), the interfacial fracture energy of Al/TiN films is predicted via finite element analysis (FEA), combined with the J-integral method and modified virtual crack closure technique (VCCT). The foregoing simulated approaches are also verified by related analytical solutions and experimental data. Moreover, the effects of several patterned types of metal lines underneath the Al/TiN interface with various embedded cracks are analyzed. The primary results highlight a significant increase in the energy release rate (G) induced by the passing of a crack along the interface of Al/TiN films through the region below a metal line with a high degree of hardness. Dielectrics with a lower modulus would have the capacity to restrain progressive crack growth. Thus, a high G is expected to drop, as simultaneously demonstrated by the present simulated methodologies.
Effects of Post-annealing and Co Interlayer Between SiN<inf>x</inf> and Cu on the Interfacial Adhesion Energy for Advanced Cu Interconnections
2020, Electronic Materials Letters

View all citing articles on Scopus

View full text

Adhesion study of low-k/Si system using 4-point bending and nanoscratch test

Abstract

Introduction

Section snippets

Experimental procedures

Results

Discussion

Conclusions

J. Microe. Eng.

Diamond Relat. Mater.

Eng. Fract. Mech.

Thin Solid Films

Int. J. Sol. Struct.

J. Appl. Phys.

Mater. Sci. Eng. A