TIM, EMMI and 3D TCAD analysis of discrete-technology SCRs
Introduction
The high USB3 data rate of 10 Gb/s requires ESD protection solutions with a capacitance lower than 0.25 pF [1]. Furthermore USB systems typically require 15 kV system level robustness (IEC 61000-4-2 [2]) which is cost inefficient to achieve by on-chip protection due to high area consumption, as the robustness of the protection device itself demands a large size to sustain the high current flow. The substrate would have to be extremely low doped to achieve the required low capacitance. Off-chip ESD protection elements based on discrete component technologies are therefore a solution [1]. Silicon controlled rectifiers (SCR) [3], [4] fulfill the above requirements. They have very low clamping voltage (< 2.5 V) and low on-resistance (< 0.3 Ω) resulting in high ESD robustness.
Recently, merit factors like ESD robustness, RF performances, as well as failure modes have been investigated for SCR test structures with triggering taps (TTs) fabricated in a dedicated discrete technology [1]. The primary goal of the introduction of TTs is the lowering of the trigger voltage since, because of the low substrate doping, the trigger voltage of SCRs without TT would be unpractically high (i.e. 70–80 V, [1]). Voltage overshoots occurring at times below 0.5 ns could also be reduced by the introduction of TTs [1]. The distance between the TTs and their width has been chosen empirically [1] to optimize the trade-off between capacitance, which rises with number of TTs, and trigger homogeneity, which depends on the speed of the on-state spreading (OSS) phenomenon after the SCR triggering [5], [6]. OSS is a 3D phenomenon occurring in devices with S-shape IV characteristics and takes place after the triggering of an initial on-state region which spreads with time [5], [7]. The rate of the transient voltage drop after triggering depends on the overall rate of the increase of the on-state region, so a larger number of TTs results in a faster voltage relaxation to the steady-state holding voltage [6].
The purpose of the present paper is to investigate the triggering behavior in SCR test structures with and without trigger taps using emission microscopy (EMMI [8]) and transient interferometric mapping (TIM [9]) techniques and to confirm the conclusions driven in Ref. 1 on the basis of electrical analysis. Furthermore we investigate the OSS phenomenon by TIM and compare the extracted spreading speed with the results of a 3D TCAD simulation. It is the first time that TIM and 3D TCAD analysis have been combined on discrete technology SCRs.
Section snippets
Experiments and simulation
The basic pnpn structure of the SCR is shown in Fig. 1. The device test structure without TT is referred to as “w/o-TT” (Fig. 1a). Here the triggering of the SCR is determined by the breakdown of the n-well/p-sub junction [1].
To decrease the trigger voltage Vt1, an additional p-type trigger diffusion (TT) is added. This structure contains 10 parallel fingers as in [1] and is referred here as “w-TT” (Fig. 1b). The breakdown in this structure takes place at the nwell/TT junction. The top layout
Results and discussion
Because of self-heating considerations, the EMMI was only performed with the w-TT device, which has a low Vt1 of 17 V, against 70 V for w/o TT. The DC up and down current sweeps in the breakdown and snapback regimes at low currents show a hysteretic behavior (Fig. 2a) typical for devices with negative differential resistance [12]. In avalanche breakdown (point A in Fig. 2a), the emission comes from the TTs as expected, see Fig. 2b. After the SCR is triggered, (point B in Fig. 2a) the emission
Conclusions
We have demonstrated that combining EMMI, TLP, TIM and 3D TCAD provides a powerful methodology for analysis and optimization of discrete technology ESD protection devices. The on-state spreading phenomenon analyzed by TIM is consistent with the results of 3D TCAD simulation. The OSS speed is in the 1–4 μm/ns range under the studied conditions both in experiments and TCAD simulations. The TCAD results provide a better understanding of OSS mechanism. The OSS front moves faster than if it were
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