A cross-layer SER analysis in the presence of PVTA variations
Introduction
As the semiconductor industry migrated to nanometer regime, radiation-induced Soft Errors began to emerge as one of the major challenges of integrated circuits [1], [2], [3], [4], [5], [6], [7], [8]. Soft error usually manifests itself as a Single Event Transient (SET) or a Single Event Upset (SEU) depending on if the victim semiconductor device is combinational or memory-type element [9]. An accurate and systematic circuit-level Soft Error Rate (SER) estimation technique is the key essential for resilient and robust designs [4], [10], [11], [12], [13]. However, besides device-level parameters which are mainly impacted by fabrication process, variations in voltage, temperature, and aging due to abrupt workload/ambient changes [14], [15] even more complicate the modeling and evaluation of soft error [16], [17], [5], [18]. To accurately address this issue, a cross-layer SER analysis technique is a necessity to bridge the gap between system-level and circuit-level by incorporating workload-dependent PVTA variations into the circuit-level SER estimation procedure.
Process, Voltage, Temperature, and Aging (PVTA) variation is one of the major dark sides of the technology scaling [19], [20], [21], [22], [23], [24]. Due to the process variations [25], [26] attributes of transistors (such as gate length, oxide thickness, diffusion depth, and variation mainly because of random dopant fluctuation) deviate from their nominal value. Temperature variations are mainly due to the workload-dependent switching, short-circuit and leakage power of transistors. Voltage variation (voltage drop) is mainly a consequence of changes in the workload-dependent supply current drawn from nonzero resistance and inductance of supply wires that lead to and , respectively. Transistor aging (e.g., NBTI, PBTI, and HCI) increases the absolute value of the threshold voltage of transistors which leads to degradation of transistors driving current over time [27], [28], [29], [30]. Note that transistor aging depends on PVT variations, logic probability (LP) and Toggling Rate (TR) of transistors which are determined based on workload [31], [27], [32], [33]. As a result of workload-dependent PVTA variations, the measured electrical properties of transistors deviate from the design specifications.
PVTA variations significantly impact susceptibility of processors components such as combinational blocks, sequential blocks and also SRAM memories. For example, from layout- and circuit-level perspectives, when a high-energy particle hits a sensitive region of a gate inside the processor core, the accumulated charge can generate a voltage glitch. The glitch propagates through the circuit and results in an error if it is captured by downstream flip-flops [9]. This process can be categorized into three different steps, namely glitch generation, glitch propagation, and glitch latching. PVTA variations can considerably impact each of these three steps; first, due to PVTA variations, electrical properties of the victim gate is changed. As a result, characteristics (i.e., width and amplitude) of the generated glitch are varied. Second, PVTA variations also impact electrical masking of the gates located on the propagation path from the victim gate to the downstream flip-flops (width and amplitude of the glitch are attenuated by the electrical properties of gates). Third, the glitch might also be masked due to the latching-window if it does not overlap with latching-window of the downstream flip-flops. Therefore, PVTA variations by affecting latching characteristics of downstream flip-flops (such as setup time), impact the latching-window and consequently SER of logic cores.
Although soft error analysis has received significant attention in recent years, to the best of our knowledge, state-of-the-art techniques lack a holistic methodology to consider and assess the combined impacts of PVTA-variations on SER. In this paper, we propose a comprehensive cross-layer approach to calculate SER of processors by taking workload-dependent PVTA variations, workload-dependent signal statistics (i.e., logic patterns), and the properties of the underlying devices into account. Fig. 1 illustrates our proposed cross-layer SER estimation methodology that spans design abstraction layers from device-level to application-level. At the application-level, it is needed to capture the temporal behavior of workloads within and across applications. Further, variations in PVTA and logic patterns are distinct across different pipeline stages and functional units. At circuit-level, there are spatial variations in PVTA, LPs, and TRs of silicon instances (i.e., gates, flip-flops, and SRAMs) across the chip. Even inside the same gate, transistors are varied and aged at different pace due to the stack effect (i.e., transistors in series structure) [27], [34]. To accurately capture the spatial and temporal variations, we propose to perform a top-down profiling from application-level to device-level to obtain the impact of higher levels of abstraction on I–V (current–voltage) characteristics of each transistor. Afterwards, based on the updated electrical properties of each transistor, a circuit-level SER estimation technique is applied to extract the workload-dependent SER of the processor. In particular, our main contributions are as follow:
- (1)
We propose a PVTA-aware cross-layer methodology for SER estimation flow that considers both high-level (workload and architecture) and low-level (layout and circuit) information.
- (2)
We consider the combined impacts of PVTA variations on SEU and SET by accurately modeling the effects of PVTA on glitch generation, glitch propagation, and glitch latching.
- (3)
Our proposed method is instance-based and time-dependent. Instance-based approach guarantees that PVTA profiles of each cell (instance) in the circuit and spatial correlation across the chip are accurately captured. Time-dependent feature assures that temporal aspects of PVTA variations are considered.
- (4)
We demonstrate the details of the proposed cross-layer methodology using a commercial microprocessor, namely LEON3 running various realistic benchmark applications.
The rest of this paper is organized as follows: Section 2 overviews the related work. Section 3 explains the effects of PVTA variations on SER. Section 4 presents the proposed cross-layer methodology. Section 5 discusses the top-down PVTA profiling. Section 6 explains the proposed PVTA-aware circuit-level SER calculation technique. Section 7 discusses the experimental results and finally, Section 8 is the conclusion of this paper.
Section snippets
SER estimation
Various techniques have been proposed to estimate SER of logics and memories [35], [36], [17], [37], [38], [39], [40], [41], [42], [43], [44], [45], [46], [47], [48], [49], [50], [16], [51], [52]. Note that SEU has been considered as the critical contributor to soft error [8], [7], however, it is believed that depending on technology, working conditions, and operating frequency, SET is also becoming important [53], [6], [35]. Although SER estimation is widely studied, only a few of
PVTA impact on soft error
This section explains how PVTA variations impact SER of SRAMs as well as logics by influencing glitch generation, glitch propagation, and latching-window masking.
Overview of the methodology
In this section, we present our proposed methodology to capture the combined effects of PVTA on SER. The key features of the proposed methodology are: (1) workload-aware, (2) layout-dependent, (3) instance-based, (4) time-dependent, and (5) cross-layer. As shown in Fig. 7, the proposed methodology consists of two blocks:
- •
Top-down PVTA profiling: in this block, for each timing window, a top-down approach is used to extract PVTA profiles of the underlying circuit. Thanks to this approach, both
Top-down PVTA profiling
For PVTA analysis, we mainly use the models/methods presented in [70], [24], [66], [67], [19], [75], [69], [32], [30], [68], [66], [80], [81], [71]. According to Fig. 7, the flow starts by cutting the application execution time into different timing windows. For each of them, we perform an application profiling based on the register transfer level or system-level models to obtain the input patterns of every functional unit in the processor [68]. Next, a gate-level logic analysis is done on top
PVTA-aware SER calculation
In this section, we present the proposed technique to compute SER of processors by taking into account the effects of the obtained PVTA profiles of each instance. Note that each individual instance in the design has a unique PVTA profile [19]. To address this issue, we use an instance-based PVTA-aware SER estimation flow [19].
Experimental setup
Several ITC’99 benchmark circuits [94] and the LEON3 processor [95] are used to evaluate the effects of PVTA variations on SER. To assess the dependency of workload-dependent PVTA variations, several benchmark applications including FIR and Adpcm from SNU Real time benchmarks [96], and Qsort, Stringsearch, FFT, Basicmath, and Dijkstra from MiBench benchmarks [97] are considered. Circuits are synthesized, placed and mapped using NANGATE 45 nm library [98]. We assume in the normal condition,
Conclusions
In this paper, we analyzed the impacts of PVTA variations on susceptibility of VLSI chips to soft error. We deeply investigated how glitch generation (i.e., critical charge), glitch propagation (electrical masking), glitch latching (setup time of flip-flops), and also SNM of SRAM cells are varied due to the workload-dependent PVTA variations. Based on that, we proposed an accurate cross-layer instance-based SER estimation methodology that takes the effects of the workload-dependent PVTA into
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