Stress analysis of Cu/low-k interconnect structure during whole Cu-CMP process using finite element method

Abstract

The stresses of Cu/low-k interconnect structure during the whole Cu-CMP process were studied based on finite element method to analyze the interfacial delamination and fracture of the low-k layer. Effects of the polishing down pressure, low-k modulus, barrier modulus, Cu film thickness, and the coefficient of friction (COF) on the stress distribution were investigated. Simulation results revealed that the probabilities of both interfacial delamination and fracture of low-k layer during all three polishing steps were raised as increasing the polishing down pressure, barrier modulus, and the COF; while increase of low-k modulus made the probabilities decreased. The COF mainly affected interfacial delamination. During bulk Cu removal step, it can be seen that the decrease of Cu thickness made the probability of interfacial delamination increased, but had little effect on the fracture of low-k layer. Among three polishing steps, it was during the barrier polishing step that the risk of interfacial delamination between barrier layer and low-k layer was the largest, at the corner of interconnect structure interface; while the probability of fracture of low-k layer was the highest during overpolishing step, at the corner of low-k layer surface. Moreover, during the same polishing step, effects of the same parameter on interfacial delamination and on fracture of low-k layer were compared.

Introduction

As the feature size of integrated circuits (ICs) continues to decrease, the resistance–capacitance (RC) time delay and the crosstalk become to be the major problem for the fabrication of new generation ICs. Therefore, low-k dielectrics and copper are introduced in order to reduce the parasitic capacitance and the resistance [1], [2]. Different from the conventional metallization technique, copper is integrated into an IC manufacturing process by using the technique of dual Damascene [3], [4], [5]. Then chemical mechanical planarization (CMP) is applied to remove the extra metal material and make the wafer surface globally planarized [6]. However, the application of low-k dielectrics has brought some problems, such as delamination and fracture of low-k material during CMP because of poor adhesion and weak mechanical strength [2], [7], [8]. The CMP-induced delamination was extensively studied by many researchers [9], [10], [11], [12]. Balakumar et al. [9] investigated the mechanism of peeling and delamination during Cu-CMP process using Cu/SiLK single and dual stack structure. Leduc et al. [12] demonstrated that CMP-induced delamination was driven by the work done against the friction force. Accordingly, some methods had been reported to reduce the CMP-induced delamination, including decrease of the CMP polishing down pressure, improvement of the mechanical strength of low-k materials, and enhancement of the adhesion strength between low-k layer and other layers. In addition to experimental researches, simulation investigations had also been performed using finite element (FE) analysis [2], [13], [14], [15]. Compared with experimental approaches, the FE method is convenient for analyzing the effects of CMP process parameters on the stress distribution of Cu/low-k interconnect structure, which is the key factor to cause the delamination and fracture of low-k layer during CMP. It is well known that there are three polishing steps for the whole Cu-CMP process, they are bulk Cu removal step, barrier polishing step, and overpolishing step [9]. The delamination and fracture of low-k layer may happen at any one step. However, most of the existing researches are focused on the bulk Cu removal step.

Consequently, in this paper, stress analysis of Cu/low-k interconnect structure during all the three polishing steps were implemented with FE method in order to thoroughly understand the effects of CMP process parameters on the delamination and fracture. The studied process parameters involved the Cu film thickness, the polishing down pressure, the low-k dielectric modulus, the barrier layer modulus, and the coefficient of friction (COF). Furthermore, the probabilities of delamination and fracture during different polishing step were compared.