Probability calculation of read failures in nano-scaled SRAM cells under process variations

doi:10.1016/j.microrel.2012.04.022

Microelectronics Reliability

Volume 52, Issue 11, November 2012, Pages 2805-2811

https://doi.org/10.1016/j.microrel.2012.04.022 Get rights and content

Abstract

In this paper, we present an accurate method for predicting the read failure probability of SRAM cells. First, using a simple I–V model for transistors, analytical expressions for the V_read and V_trip of SRAM cells are obtained. These expressions are subsequently used to derive a fairly accurate model for the read margin of SRAM cells. Then, using Jacobian determinant, the joint probability density function for the V_read and V_trip is calculated without assuming any specific distribution function for its probability. The accuracy of the approach is studied by comparing its results with those of previous techniques and standard Monte Carlo simulations for 32 and 45 nm CMOS technologies. Compared to these techniques, our approach has a considerably lower error at the price of slightly increasing the computation time or is much faster at the cost of marginally decreasing the accuracy. In addition, the method has the advantage of not being restricted to a specific probability distribution form.

Introduction

Process variations have had a large impact on performance and functionality of nano-scaled Static Random Access Memory (SRAM) cells. Predicting the statistical distribution of parameters due to process variations is critical in modern digital designs where a large number of memory cells are employed. The requirements for these designs include assuring reliability for high accuracy in the presence of parameter variations [1].

SRAM cell failures can occur due to an increase in the cell access time (access time failure), unstable read (flipping of the cell data while reading) and/or write problems (inability to successfully write to a cell). These failures are collectively referred to as read/write failures. SRAM cell failures can also occur due to a failure in the data holding capability of the cell, specially, flipping of the cell data with the application of a supply voltage lower than the nominal one in the standby mode (known as hold failure in the standby mode). The aforesaid cell failures may be caused by variations in the device parameters, and hence, are commonly called parametric failures [2], [3]. The focus of this work is on the read failure.

There are a number of previous works which have concentrated on read failure probability of SRAMs as a result of process variations. Some works like [4], [5] present only analyses of the read failure rate of SRAMs without attempting to model it. The work presented in [6] suggested a methodology for analyzing the SRAM cell stability. Since no closed-form expressions were given, it might not be appropriate for the process variations analysis. In [7], the author presents a generic method for analyzing the effect of process variability in nano-scale circuits. The proposed approach uses kernel and a generic tail probability estimator to eliminate a-priori density choice for the variations of circuit. However, the proposed approach does not provide closed-form expressions for the read failure probability. There are also some efforts, like [8], which present modeling techniques to estimate the read failure probability of SRAM. In [8], a technique based on piecewise modeling and controlled sampling is presented. In contrast, our proposed approach relies on a direct model for the read failure probability calculation based on variations of instance parameters, which are circuit parameters explicitly provided in the netlist of SPICE and the associated transistor parameters such as the transistor width, length, oxide thickness and threshold voltage.

A work that directly addresses the read failure probability of SRAM cell is reported in [9]. In this work, the authors assumed a Gaussian distribution function for the variation of the target parameter of interest. It used complex device models (non-square-law models) to obtain the read margin using numerical methods. The square-law models augmented by short-channel MOSFET models were also presented as an alternative to the numerical approach to reduce the computation time. The latter approach affects the accuracy. Note that the square-law model is not valid for sub-65 nm technology. There have been other works like [10], [11] which make use of simulation-based techniques to capture the SRAM read failure probability. The proposed method in these works, which is called importance sampling, reduces the computation time of the standard Monte Carlo-based approach.

In this paper, first we propose an accurate analytical model for the read margin. Based on that, we invoke a general framework for obtaining the read failure probability of the SRAM cells without assuming any specific form for its distribution which increases the accuracy. The computation time of the approach is also small. To the best of our knowledge, no such modeling framework has been developed before. The rest of the paper is organized as follows. In Section 2, a transistor I–V model and the derivation of the analytical expressions for the SRAM cell V_read and V_trip based on the model are discussed. Section 3 presents the suggested approach for calculating the joint probability distribution function of the V_read and V_trip which results in finding read failure probability. Simulation results are discussed in Section 4 whereas Section 5 concludes the paper.

Section snippets

Methodology

The read failure occurs due to the corruption of the stored data in the cell while accessing it. During the read operation of the cell shown in Fig. 1a (VL = “1” and VR = “0”), the voltage at node R (VR) increases to a positive value, denoted by V_read. In this mode, the bitline BL is set to V_DD, while the node VR is connected to the ground via the right pull down transistor (NR) which is ON. The voltage difference between BL and ground drops across right access transistor (AR) and NR. The voltage

Distribution function of read failure probability

In order to calculate the read failure rate, the probability that the V_read is larger than the V_trip of SRAM cell should be calculated. The following expression is the mathematical representation of read failure probability $Read Failure Probability = P (RM 0 > (V_{trip} - V_{read} \equiv RM)) = \int_{0}^{V_{dd}} \int_{0}^{V_{read} + RM 0} {fV}_{read}, V_{trip} (V_{read}, V_{trip}) \cdot {dV}_{trip} \cdot {dV}_{read}$ where RM0 is the minimum needed read margin. The value of RM0 depends on the working environment of the memory cell. In noisy areas this value is larger. It should be noted

Results and discussion

In this section, the accuracy of the proposed models for calculating V_read and V_trip is studied. Also, the effectiveness of our proposed methodology for calculating the joint probability density function is compared to that of the work presented [9]. Fig. 4 shows the comparison between V_trip and V_read of the SRAM cell versus the β ratio for both our proposed model (Eqs. (8), (15)) and simulation for the 45 nm technology. This shows a very good accuracy for the model. Next, we discuss the

Conclusion

We proposed a methodology for modeling the read failure of SRAM cell under process variations. The proposed method presented a general framework where there was no limitation on the distribution function of the varying parameter of interest. First, a simple yet fairly accurate I–V model was used to derive the read and trip voltages analytically.

Then, using a technique based on Jacobian determinant, the joint probability distribution function of read and trip voltage was calculated. Based on

References (24)

International technology roadmap for semiconductors....
Mukhopadhyay S, Mahmoodi H, Roy K. Modeling and estimation of failure probability due to parameter variation in...
Mukhopadhyay S, Mahmoodi H, Roy K. Statistical design and optimization of SRAM cell for yield enhancement. In: Proc int...
Z. Guo et al.
Large-scale SRAM variability characterization in 45 nm CMOS
IEEE J Solid-State Circ
(2009)
Tsai C, Marek-Sadowska M. Analysis of process variation’s effect on SRAM’s read stability. In: Proc international...
Agarwal K, Nassif S. Statistical analysis of SRAM cell stability. In: Proc design automation conference; 2006. p....
Mukhopadhyay S. A generic method for variability analysis of nanoscale circuits. In: Proc integrated circuit design and...
Wang J, Yaldiz S, Li X, Pileggi LT. SRAM parametric failure analysis. In: Proc. design automation conference; 2009. p....
S. Mukhopadhyay et al.
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
IEEE Trans Comput-Aided Des Integr Circ Syst
(2005)
Doorn T, Ter maten E, Croon J, Di Bucchianico A, Wittich O. Importance sampling monte carlo simulations for accurate...

Kanj R, Joshi R, Nassif S. Mixture importance sampling and its application to the analysis of SRAM designs in the...

A. Khakifirooz et al.

A simple semiempirical short-channel MOSFET current–voltage model continuous across all regions of operation and employing only physical parameters

IEEE Trans Electron Dev

(2009)

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