Elsevier

Microelectronics Reliability

Volume 51, Issues 9–11, September–November 2011, Pages 1624-1631
Microelectronics Reliability

The combinational or selective usage of the laser SQUID microscope, the non-bias laser terahertz emission microscope, and fault simulations in non-electrical-contact fault localization

https://doi.org/10.1016/j.microrel.2011.06.060Get rights and content

Abstract

Recently, in the field of fault localization of LSI chips, several non-electrical contact techniques have been proposed. The techniques include the laser SQUID microscope (L-SQ) and the non-bias laser terahertz emission microscope (NB-LTEM). Both techniques have pros and cons. The L-SQ, for examples, can localize open defects in some cases, but it requires closed circuit. The NB-LTEM can localize open defects and short defects, and not requires closed circuit. The NB-LTEM, however, cannot localize open defects in some cases. The fault simulation specially designed for the L-SQ or the NB-LTEM makes it precise or efficient to localize defects. The combinational or selective usage of the L-SQ, the NB-LTEM and the related simulations makes it possible to localize defects in many cases. In this paper, we would like to review our results and organize them from the viewpoint of failure mode and defect sites.

Highlights

► In LSI chip failure analysis, fault isolation is one of the most important steps. ► We have developed L-SQ and NB-LTEM, as no electrical contact fault isolation tools. ► Laser SQUID microscope (L-SQ), no bias laser terahertz emission microscope (NB-LTEM). ► Combo use of L-SQ, NB-LTEM, and their simulators is useful in LSI fault isolation. ► Many cases of fault isolation using these tools have been demonstrated.

Introduction

The steps of LSI chip failure analysis are shown in Fig. 1.

The first step is the fault diagnosis. In the fault diagnosis step, we use only electrical test tools and software. The second step is the nondestructive (ND) fault localization. In the ND step, we use infrared optical beam induced resistance change (IR-OBIRCH), photo-emission microscope (PEM), etc. The third step is the Semi-D (destructive) fault localization. In the Semi-D step, we use nano-probing tools, resistive contrast imaging (RCI) method using electron beam absorbed current (EBAC), etc. The final step is destructive physical analysis. In the final step, we use focused ion beam (FIB), transmission electron microscope (TEM), etc.

The non-electrical-contact failure analysis tools such as the laser superconducting quantum interference device (SQUID) microscope (L-SQ) and the non-bias laser terahertz emission microscope (NB-LTEM) are categorized in the second (ND localization) step (Fig. 1). The L-SQ and the NB-LTEM do not require Vdd-bias and signal input. Also, they do not require signal output via electrodes. Therefore, they do not require electrical contact.

The main merits of using them, compared to using conventional ND tools, are as follows:

  • We can use them before the end of wafer processing: fast feedback is possible.

  • We can use them without troublesome pin handling and/or mechanical probing: efficient analysis is possible.

As a non-electrical-contact failure analysis tool, we have first developed the L-SQ [1], [2], [3], [4]. Using the L-SQ, we have succeeded to localize the open defects of common Vdd and GND lines. We could not, however, localize the open defects of individual Vdd/GND lines and signal lines. Also, we could not localize short defects of signal lines.

In order to overcome this issue, we have secondly developed the NB-LTEM system. Using the NB-LTEM, we have succeeded to localize these defects [5], [6], [7], [8], [9], [10].

In this paper, we would like to organize these our results from the viewpoint of failure mode and defect sites.

Section snippets

Basic concept of the L-SQ

Fig. 2 shows basic concept of the L-SQ. Continuous laser beam with wavelength of 1.06 μm is irradiated from the backside of the LSI chip. When the laser beam is irradiated at a p–n junction, a photocurrent is induced resulting magnetic flux generation. The magnetic flux is detected by the SQUID magnetometer, located above the LSI chip. The SQUID magnetometer is made from high Tc DC-SQUID.

System of the L-SQ

Fig. 3 shows schematic of the L-SQ system. Not only the sample stage but also the SQUID magnetometer can be

Basic concept of NB-LTEM

Fig. 9a and b shows the basic concept of conventional LTEM and the NB-LTEM, respectively. The conventional LTEM requires Vdd bias and, in some cases, input signal as shown in Fig. 9a [12], [13]. The NB-LTEM does not require Vdd bias and input signal. Both methods do not require signal output via electrodes.

In Fig. 9b showing the NB-LTEM, a femtosecond laser beam is focused near chip surface from the backside of an LSI chip. We use a 1.06 μm wavelength laser beam so that it transmit through Si

Combinational or selective usage of L-SQ, NB-LTEM and related simulations

Table 1 shows the review results organized from the viewpoint of failure modes and defect sites.

Using the L-SQ, we have localized the open defects of common Vdd and GND lines without simulation (Fig. 4, Ref. [3]). Using the L-SQ (+S-SQUID) with simulation, we have demonstrated to localize short defect between a signal line and an individual GND line (Fig. 7, Fig. 8).

Using the NB-LTEM, we have localized the open defects of individual GND lines and signal lines without simulation (Fig. 14, Fig. 15

Summary

We have developed the L-SQ, the NB-LTEM, and the related simulators. We have applied them to the simple test structures and the actual circuits.

The application results to simple test structures showed that the terahertz waveforms change with the metal line length and the open position.

Application results of the defect localization at the actual circuits are organized from the viewpoint of failure modes and defect sites. It showed that we could localize most of the defects in open and short

Acknowledgments

The authors would like to thank Hiroki Kitagawa, Yoshimitsu Aoki and Shouji Inoue for the sample preparation and measurement. The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center, the University of Tokyo. This work was supported by SENTAN, Japan Science and Technology Agency, Japan.

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