Influence of the manufacturing process on the electrical properties of thin (<4 nm) Hafnium based high-k stacks observed with CAFM
Introduction
The replacement of SiO2 by high-k materials in CMOS devices will allow reaching the required equivalent oxide thickness (EOT), but with a larger physical oxide thickness, which reduces the leakage current drastically. However, the SiO2 substitute must provide suitable values of dielectric constant and barrier height, and a high quality interface with the Si substrate. Moreover, it must be thermodynamically stable on Si and compatible with the gate material and the high temperature CMOS processes [1].
Most of the knowledge about the electrical behavior of high-k materials has been gained from measurements performed on macroscopic MOS capacitors or transistors [2], [3], [4] using standard electrical characterization methods at wafer level. This kind of tests, however, provides partially averaged information on the electrical properties of the material. On the contrary, Conductive Atomic Force Microscope (CAFM), as demonstrated for SiO2 and Hafnium based high-k materials [5], [6], [7], [8], is able to characterize the gate dielectric at a nanometer scale, showing properties to which the standard techniques are blind. In this work, CAFM is used to study at this scale the electrical behavior of HfO2, HfSiO and HfO2/SiO2 gate dielectrics as a function of the post-deposition annealing temperature (TA), percent of Hafnium content and physical thickness of the stack.
Section snippets
Experimental
The samples consisted of four different high-k materials: 2 nm HfO2, 2 nm Hf (60%) SiO, 2 nm Hf (80%) SiO and 4 nm Hf (80%) SiO on top of a Silicon n-type substrate, with a nominal 1 nm thick chemical SiO2 interfacial layer. For each high-k material, eight wafers subjected to post-deposition annealing processes at different temperatures (600 °C, 700 °C, 800 °C, 850 °C, 900 °C, 950 °C, 1000 °C and 1050 °C) have been provided. One wafer without annealing process, for each high-k material type, has been kept
Results and discussion
We will start investigating the electrical conduction of the different samples by measuring I–V curves at different positions of the stacks. Fig. 1 shows an example of I–V curves measured on 2 nm (a) and 4 nm (b) Hf (80%) SiO subjected to an annealing process at 600 °C. Note that, once we are above the noise level, for a fixed voltage, larger currents (in absolute value) are measured for the 2 nm thick layer, which suggests a larger conductivity of these films, as expected.
To quantify and compare
Conclusions
The conductivity of Hafnium based high-k materials have been studied at nanometer scale using CAFM to analyze the impact of composition, annealing temperature and layer thickness. I–V curves show that higher annealing temperature (but below 1000 °C), larger physical thickness and higher Hafnium concentration improve the materials electrical resistance. Moreover, the large lateral resolution of the technique has allowed analyzing the conduction homogeneity of the layers. The standard deviation of
Acknowledgements
The authors thank Raimund Foerg, Karl Hofmann and Martin Kerber, Infineon Technologies, and Wouter Polspoel, IMEC, for helpful discussions. This work has been partially supported by the Spanish MEC (TEC2004-00798/MIC research project), the DURSI of the Generalitat de Catalunya (2005SGR-00061) and the Erasmus Exchange Program between DEG and UAB.
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