The impact of PMOST bias-temperature degradation on logic circuit reliability performance

Abstract

This work investigated the impact of pMOST bias-temperature (BT) degradation on logic product's speed (F_max) and minimum allowed operating voltage (V_ccmin). BT degradation occurs during the product Burn-In and under the normal circuit operation. The interaction of device degradation and circuit performance is explained. Fluorine implants after poly etch and before hard-mask removal are utilized to separate out the BT instability effects from other reliability degradations. Physical mechanism and degradation models are proposed to explain the interaction of fluorine with device and circuit reliability. Process optimization, such as fluorine implant, can be used to reduce the pMOST BT impact on circuit degradation. Reliability guardband in F_max and V_ccmin is recommended, as part of the production testing to ensure reliable logic product performance and functionality during the product's lifetime. A guardband methodology is also discussed in the paper.

Introduction

During product Burn-In (BI) and normal circuit operation, n and pMOS transistors are susceptible to Si/SiO₂ interface state generation and oxide bulk charge trapping [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14]. These effects translate to device threshold voltage (V_t) and drive current (I_on) shifts, and, in turn, they affect circuit propagation delay and functionality. There are many mechanisms responsible for the device degradation, depends on the nature of stress. Among the various mechanisms, one is the pMOST bias-temperature (PBT) degradation or negative bias-temperature instability (NBTI). BT degradation is worse on pMOST than nMOST, primarily due to the presence of holes, in the pMOST inversion layer [1], [2], [3], [4], [5], [6], [7], [8], [9], [10] that are known to interact with the oxide states. Extensive study has been conducted to understand the PBT effect on discrete capacitors [1], [2], [3] and transistors [4], [5], [6], [7], [8], [9], [10]. However, there have been no detailed reports on the product impact. This may not be an issue in the past because of the change in device V_t and I_on is small for device technology with relative longer channel length and thicker gate oxide. As technology is scaled and the power supply voltage drops, this V_t and I_on shift is a larger percentage of the gate overdrive, and results in a larger performance impact. Data on discrete devices and ring oscillators [4], [5], [6], [7], [8], [9], [10], [11] of recent technologies have suggested that the shifts induced by PBT stress are one of the dominant degradation mechanisms in product operation. This raised the need to better understand PBT instability and quantify its effect on circuit reliability.

From reliability point of view, we can generate the discrete transistor based BT degradation guideline as a general design rule for pMOST, and construct a TCAD tool for circuit degradation projection. The problem is models for pMOST (and nMOST) degradation are only roughly accurate and the circuit simulations are also subject to process variability. In addition, there are key parameters, such as circuit activity factor, that are a function of the customer applications and are not easy to quantify. This leaves the only option to ensure proper circuit performance is to minimize reliability degradation by optimizing the process and building-in sufficient margin in the design. Unfortunately, other than designing circuits to be independent of the signal rising edge, there is no known method to design-in reduced PBT instability sensitivity. Moreover, since some of the PBT degradation recovers under AC operation, it is quite difficult, if not impossible, to quantify the actual product impact or to simulate the circuit degradation based on the DC quasi-static model assumptions. All the above says that it is important to collect product data to validate the design and to ensure that we are not adding unnecessary or stringent rules that minimize the circuit performance. The product data can also be used to understand the circuit behavior and to set a proper test guardband for the product.

In order to quantify the impact of pMOST BT (or NBTI) on circuit degradation, we need to find a process that can distinguish the BT degradation from other reliability mechanisms such as nMOST hot-carrier (NHC) or oxide TDDB. In this paper, we use fluorine implant to characterize the PBT effect on devices and link its effect to the circuit reliability degradation. Fluorine has been utilized extensively in recent VLSI processing for its bond strength with silicon [11] and its ability to minimize boron transient-enhanced diffusion (TED) effect [12], [13]. Fluorine, in the form of BF₂ and F ion, can be introduced into the oxide at S/D, LDD (or S/D-extension) and gate implant steps. Incorporation of fluorine reduces PBT degradation [5], [7] and improves NHC resistance. However, fluorine also enhances boron penetration and increases gate oxide thickness (T_ox) [12], [14]. Therefore, the PBT improvement by fluorine may also come from the oxide T_ox increase or the reduced electric-field stress. In our study, fluorine implant after poly etch and before poly hard-mask (HM) removal was used to minimize the boron penetration and the T_ox difference. We compared various reliability degradation mechanisms with the product Burn-In degradation, and showed that PBT is one of the key factors responsible for the product degradation. Based on the degradation characteristics, a guardband methodology is proposed to ensure parts are reliable after the lifetime operation.