The impact of PMOST bias-temperature degradation on logic circuit reliability performance
Introduction
During product Burn-In (BI) and normal circuit operation, n and pMOS transistors are susceptible to Si/SiO2 interface state generation and oxide bulk charge trapping [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14]. These effects translate to device threshold voltage (Vt) and drive current (Ion) shifts, and, in turn, they affect circuit propagation delay and functionality. There are many mechanisms responsible for the device degradation, depends on the nature of stress. Among the various mechanisms, one is the pMOST bias-temperature (PBT) degradation or negative bias-temperature instability (NBTI). BT degradation is worse on pMOST than nMOST, primarily due to the presence of holes, in the pMOST inversion layer [1], [2], [3], [4], [5], [6], [7], [8], [9], [10] that are known to interact with the oxide states. Extensive study has been conducted to understand the PBT effect on discrete capacitors [1], [2], [3] and transistors [4], [5], [6], [7], [8], [9], [10]. However, there have been no detailed reports on the product impact. This may not be an issue in the past because of the change in device Vt and Ion is small for device technology with relative longer channel length and thicker gate oxide. As technology is scaled and the power supply voltage drops, this Vt and Ion shift is a larger percentage of the gate overdrive, and results in a larger performance impact. Data on discrete devices and ring oscillators [4], [5], [6], [7], [8], [9], [10], [11] of recent technologies have suggested that the shifts induced by PBT stress are one of the dominant degradation mechanisms in product operation. This raised the need to better understand PBT instability and quantify its effect on circuit reliability.
From reliability point of view, we can generate the discrete transistor based BT degradation guideline as a general design rule for pMOST, and construct a TCAD tool for circuit degradation projection. The problem is models for pMOST (and nMOST) degradation are only roughly accurate and the circuit simulations are also subject to process variability. In addition, there are key parameters, such as circuit activity factor, that are a function of the customer applications and are not easy to quantify. This leaves the only option to ensure proper circuit performance is to minimize reliability degradation by optimizing the process and building-in sufficient margin in the design. Unfortunately, other than designing circuits to be independent of the signal rising edge, there is no known method to design-in reduced PBT instability sensitivity. Moreover, since some of the PBT degradation recovers under AC operation, it is quite difficult, if not impossible, to quantify the actual product impact or to simulate the circuit degradation based on the DC quasi-static model assumptions. All the above says that it is important to collect product data to validate the design and to ensure that we are not adding unnecessary or stringent rules that minimize the circuit performance. The product data can also be used to understand the circuit behavior and to set a proper test guardband for the product.
In order to quantify the impact of pMOST BT (or NBTI) on circuit degradation, we need to find a process that can distinguish the BT degradation from other reliability mechanisms such as nMOST hot-carrier (NHC) or oxide TDDB. In this paper, we use fluorine implant to characterize the PBT effect on devices and link its effect to the circuit reliability degradation. Fluorine has been utilized extensively in recent VLSI processing for its bond strength with silicon [11] and its ability to minimize boron transient-enhanced diffusion (TED) effect [12], [13]. Fluorine, in the form of BF2 and F ion, can be introduced into the oxide at S/D, LDD (or S/D-extension) and gate implant steps. Incorporation of fluorine reduces PBT degradation [5], [7] and improves NHC resistance. However, fluorine also enhances boron penetration and increases gate oxide thickness (Tox) [12], [14]. Therefore, the PBT improvement by fluorine may also come from the oxide Tox increase or the reduced electric-field stress. In our study, fluorine implant after poly etch and before poly hard-mask (HM) removal was used to minimize the boron penetration and the Tox difference. We compared various reliability degradation mechanisms with the product Burn-In degradation, and showed that PBT is one of the key factors responsible for the product degradation. Based on the degradation characteristics, a guardband methodology is proposed to ensure parts are reliable after the lifetime operation.
Section snippets
Experimental
The devices used were fabricated with standard front-end transistor features such as STI, shallow S/D extensions, halo implant, thermally grown gate oxides, and salicided poly [15], [16]. Fluorine implants had different doses. A split with no fluorine was used as the control split. Both devices and microprocessor products received the complete back-end processes with six-layer Cu metals and passivation. Microprocessor units were packaged using the standard industry packaging steps.
Oxide TDDB,
Product reliability characterization
In the microprocessor, a speed path represents the circuitry encompassing the data path for the execution of one complete instruction. A simple block diagram of a product speed path is shown in Fig. 1. It is composed of the data path, stretching between a `sending latch' and a `receiving latch'. The individual gates shown in Fig. 1 are inverters, but could be any of a large number of different gate types. Data is passed through the sending latch by the arrival of a clock edge and must propagate
Results and discussion
Thanks to poly hard-mask, which blocks most of the fluorine, the implant channeling tail is significantly reduced in hard-mask and poly films than in Si [18]. However, the increasing of fluorine implant in the gate oxide can still be seen from the slightly thicker Tox and higher V, (Fig. 8). This effect also translates to the reduced S/D overlap capacitance (Cov) and lower Ion, as shown in Fig. 9. From device enhancement point of view, a better drive current and a lower overlap capacitance are
Reliability guardband for P-channel stability
During product operation, degradation of product speed below the operating frequency specified to the customer can result in product failure in the field. As a result, the way to avoid field failure is to make sure that the product works at a speed higher than that specified to the customer. The difference between this actual maximum operating frequency and that at which it is sold is called the reliability test guardband. This is different from the quality test guardband, which is designed to
Conclusions
This study demonstrated the pMOST BT effect on product reliability degradation. Fluorine implant can be used to reduce BT degradation. Reliability guardband on Fmax and Vccmin may be applied to product to ensure the required circuit performance for the lifetime operation. A test guardband should include both nMOST and pMOST components of the degradation.
Acknowledgements
The authors would like to acknowledge Babak Sabi, Sam Hu, Max Wei, Robert Kwasnick, and Mohsen Alavi for their enlightening discussions and careful review of this paper.
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