Impact of device geometry and doping strategy on linearity and RF performance in Si/SiGe MODFETs

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Abstract

Based on careful calibration in respect of 70 nm n-type strained Si channel Si/SiGe modulation doped FETs (MODFETs) fabricated by Daimler Chrysler, numerical simulations have been used to study the impact of the device geometry and various doping strategies on device performance and linearity. Both the lateral and vertical layer structures are crucial to achieve high RF performance or high linearity. The simulations suggest that gate length scaling helps to achieve higher RF performance, but degrades the linearity. Doped channel devices are found to be promising for high linearity applications. Trade-off design strategies are required for reconciling the demands of high device performance and high linearity simultaneously.

Introduction

High mobility Si/SiGe MODFETs have been widely studied for high frequency and low-noise applications. Similar to their III–V counterparts, the Si/SiGe MODFETs have a strained channel which enables high mobility and high sheet carrier density. Moreover, the compatibility of Si/SiGe MODFETs with existing Si technology makes them promising candidates for system-on-chip applications. 100 nm gate length Si/SiGe MODFETs with cut-off frequency, fT, of 74 GHz and maximum oscillation frequencies, fmax of 188 GHz at room temperature, have been successfully demonstrated [1], [2]. However, little work has been done to optimize such devices for communication applications, bearing in mind that power amplification for wideband communications requires high linearity to minimize the intermodulation distortion.

In this paper, we use numerical simulations to optimize the Si/SiGe MODFET device architecture for high linearity RF applications. The simulations are based on extensive calibration in respect of a 70 nm n-type buried strained Si channel Si/SiGe MODFET fabricated by Daimler Chrysler. Device linearity is found to be sensitive to the doping strategy, the vertical layer structure and the lateral device design. In agreement with previously published work on III–V HEMTs [3], we have found that the doped channel devices have better linearity compared to their side-doped counterparts. However, channel doping reduces the electron mobility within the channel resulting in lower drive current, along with reduced transconductance and RF performance. This requires a careful trade-off design balancing between high RF performance and high linearity. We have also carried out a scaling study based on our previous work [4]. The simulations show that the proper scaling results in improved RF performance, but has a negative impact on the linearity.

Section snippets

Device structure

This work is based on a comprehensive calibration of a 70 nm n-type Si/SiGe MODFET. The layer sequence of the calibrated device is a p− substrate with ρ>1000 Ωcm; a relaxed SiGe buffer with linearly graded Ge content up to 45%; a 5-nm SiGe supply layer with a dopant concentration of 2.5 × 1018 cm−3; a 3.5-nm SiGe spacer; the 9-nm strained Si channel; a 3-nm SiGe spacer; a 5-nm SiGe supply layer with a doping level of 1.0 × 1019 cm−3; a 6-nm SiGe cap layer and a 2-nm Si cap layer. The T-shape Au/Pt

Simulation methodology

The comprehensive calibration in respect of the 70 nm device precedes this simulation study. Simulations are carried out using the drift-diffusion device simulator MEDICI [5]. Poisson–Schrödinger solutions have been used to understand properly aspects of the device operation related to quantum confinement in the channel. The calibration starts with the ID–VG characteristics at low drain voltage which help to adjust the low field mobility parameters. This is followed by matching the ID–VG and ID–

Effect of vertical device structure

In the investigation of Si/SiGe MODFETs, improving the performance necessitates the optimization of device geometry in order to achieve better quantum confinement and good modulation efficiency, resulting in high density and high mobility of the carriers in the channel [4], [13], [14]. However, the existence of low-mobility parasitic conduction paths in these devices limits the device performance and range of operation. At high current levels, the carrier density in the low mobility slab doping

Channel doping strategies

Parallel parasitic channel conduction of the MODFETs is the major factor that affects linearity. The carriers supplied by the side doping layers may move from the channel to the low mobility parasitic conduction path at high gate voltages, which narrows the transconductance peak and reduces the linearity.

Existing work on III–V HEMTs has suggested that the introduction of channel doping improves linearity [3]. Transferring this idea into the Si/SiGe MODFETs, we also expect an increased linearity

Conclusion

We have studied the RF performance and the linearity in various Si/SiGe MODFETs architectures. The gate-to-channel separation and gate to source/drain distances were found to have significant but opposite effects on device performance and linearity. The simulations show that scaling helps to improve RF performance, but reduces slightly the device linearity. The doped channel device exhibits the best linearity but at the expense of reduced drive current, transconductance and RF performance.

Acknowledgements

This work was supported by EPSRC UK HMOS II, under grant number: GR/N65677/01.

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