A BiNoC architecture—aware task allocation and communication scheduling scheme
Introduction
In a Many-Core Network-on-Chips (MC-NoC) [1], [2], [3], chip real estate is partitioned into a two-dimensional array of rectangular processor cores. Between the cores, a mesh-configured on-chip network (i.e., Network-on-Chip, NoC) [4], [5] provides the underlying communication infrastructure. Computation tasks are allocated to individual cores and data packets are routed among different cores via the NoC fabric. Communication between cores at a distance would incur multi-hop routing and may be delayed due to traffic congestion. Hence, while it is imperative to allocate as many cores as possible to boost the parallelism, the communication overhead due to the constrained NoC infrastructure must be taken into account to achieve overall performance optimization.
Existing NoC architectures that use unidirectional links between on-chip routers offers rather limited communication capacity for applications where long streams of data must be transmitted from one processor core to the other in one direction only. The limited bandwidth often causes prolonged packet transmission delay, compromising the overall performance of multi-core computation. Recently, a novel Bidirectional Network-on-Chip (BiNoC) architecture [6], [7], [8], [9], [10] has been proposed. Since the transmission direction of a link can be reversed in a BiNoC, it has been shown that the communication capacity can be significantly improved. None the less, these earlier works focused on how to control a BiNoC fabric for a given trace of inter-processor communication requirements. For most real-world applications, the communication patterns over the NoC fabric depend very much on how specific tasks are allocated to individual processor cores, and how the computation of individual tasks are scheduled.
In this work, we focus our efforts on investigating the intertwined relations between task allocation and communication scheduling and the underlying NoC control on a BiNoC platform. We have made the following tangible contributions:
- (1)
Our integrated algorithm performs both task allocation and communication scheduling. Not only individual task is allocated to specific processor core, but its execution time also takes into account the routing path and data transmission delay over the underlying BiNoC network.
- (2)
A flexible communication delay model over a BiNoC infrastructure is proposed, where the inter-core communication delay is explicitly modelled based on specific routing path and routing direction assignment.
- (3)
Joint optimization between task allocation and communication scheduling is realized in a refinement process.
- (4)
Application of hardware (BiNoC routing and control) and software (task allocation, communication scheduling) co-design facilitates a full exploitation of the flexibility afforded by the BiNoC to enhance multi-core task allocation and communication scheduling.
The remainder of this paper is organized as follows. We first introduce the preliminary aspects of the task allocation and communication scheduling problem for BiNoC architecture in Section 2. In Section 3, we present our proposed design methodology in detail. Section 4 reports extensive experimental results using Task Graphs For Free (TGFF) standard benchmark. Finally, we conclude the paper in Section 5.
Section snippets
Background
In this section, we will first introduce an intelligent NoC architecture which is called “Bidirectional Network-on-Chip” (BiNoC). Then previous works related to task allocation and communication scheduling will be reviewed. Lastly, some application specified problems will be defined and to be solved.
Design methodology
In this section, we will provide a detailed introduction for each component in our proposed design methodology. The task allocation and communication scheduling issues can be best solved by a statistical self-study framework as introduced in this section.
Experimental results
In this section, we will evaluate the effectiveness of our task allocation and communication scheme. The experiments of evaluation consist of three parts: First, the preliminary experimental results demonstrate the performance difference between the conventional Earliest Deadline First (EDF) algorithm and our proposed method. Secondly, the performance enhancement specifically caused by the proposed refinement process is identified. At last, a hardware evaluation is applied to verify the
Conclusion
In this paper, we proposed a task allocation and communication scheduling scheme on a Many-Core Network-on-Chip system based on the distinctive Bidirectional NoC (BiNoC) architecture. The proposed BiNoC-aware method considers both task allocation and communication scheduling to avoid traffic congestions on the bidirectional network. Additionally, a refinement process is designed to further improve the system performance by reducing data transmission time on the critical path. Experimental
Acknowledgments
This work was supported by the Ministry of Science and Technology under grants MOST 104-2221-E-324-001-MY2 and MOST 104-2218-E-002-002.
Wen-Chung Tsai received the B.S. degree in computer science and information engineering from Tamkang University in 1996. He received the M.S. degree in Electrical Engineering from National Cheng Kung University in 1998. He received the Ph.D. degree in Electronics Engineering from National Taiwan University in 2011. In 2000, he joined VIA Technologies in development of Network System-on-Chip (SoC) products, and then became the digital IC design department manager. During 2011 to 2013, he was a
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Cited by (0)
Wen-Chung Tsai received the B.S. degree in computer science and information engineering from Tamkang University in 1996. He received the M.S. degree in Electrical Engineering from National Cheng Kung University in 1998. He received the Ph.D. degree in Electronics Engineering from National Taiwan University in 2011. In 2000, he joined VIA Technologies in development of Network System-on-Chip (SoC) products, and then became the digital IC design department manager. During 2011 to 2013, he was a researcher at Industrial Technology Research Institute of Taiwan and focuses on, but not limited to 4G/LTE (Long Term Evolution) researches. Dr. Tsai is currently a faculty of Department of Information and Communication Engineering, Chaoyang University of Technology.
Wei-De Chen received the B.S. degree in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2008. He received the M.S. degree in Electronics Engineering from National Taiwan University in 2010. He joined MediaTek Inc., Hsinchu, Taiwan in 2010.
Ying-Cherng Lan received the B.S. degree in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2005. He received the Ph.D. degree in Electronics Engineering from National Taiwan University in 2011. His current research interests focus on the design methodologies and algorithms for on-chip communication network architecture.
Yu-Hen Hu received the B.S.E.E. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., in 1976, and the M.S.E.E. and Ph.D. degrees from the University of Southern California, Los Angeles, in 1980, and 1982, respectively. From 1983 to 1987, he was an Assistant Professor with the Electrical Engineering Department, Southern Methodist University, Dallas, TX. Since 1987, he has been in the Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, where he is currently a Professor. He has served as an Associate Editor for the European Journal of Applied Signal Processing and Journal of VLSI Signal Processing. He has broad research interests ranging from design and implementation of signal processing algorithms, computer-aided design and physical design of VLSI, pattern classification and machine learning algorithms, and image and signal processing in general. He has published more than 200 technical papers and edited several books in these areas. Dr. Hu has served as an Associate Editor for the IEEE Transactions of Acoustic, Speech, and Signal Processing, IEEE Signal Processing Letters, and IEEE Multimedia Magazine. He has served as the Secretary and an executive committee member of the IEEE Signal Processing Society, a board of governors of the IEEE Neural Network Council representing the Signal Processing Society, the Chair of the Signal Processing Society Neural Network for Signal Processing Technical Committee, and the Chair of the IEEE Signal Processing Society Multimedia Signal Processing Technical Committee (2004–2005). He is also a steering committee member of the International Conference of Multimedia and Expo, IEEE Transactions on Multimedia on behalf of the IEEE Signal Processing Society. Professor Hu is a fellow of IEEE.
Sao-Jie Chen received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, ROC, in 1977 and 1982 respectively, and the Ph.D. degree in electrical engineering from Southern Methodist University, Dallas, USA, in 1988. Since 1982, he has been a member of the faculty in the Department of Electrical Engineering, National Taiwan University, where he is currently a full professor. During the fall of 1999, he was a visiting professor in the Department of Computer Science and Engineering, University of California, San Diego, USA. During the fall of 2003, he held an academic visitor position in the Department of System Level Design, IBM Thomas J. Watson Research Center, Yorktown Heights, New York, USA. He obtained the “Outstanding Electrical Engineering Processor Award” by the Chinese Institute of Electrical Engineering in December 2003 to recognize his excellent contributions to EE education. During the falls of 2004 to 2009, he was a visiting professor in the Department of Electrical and Computer Engineering, University of Wisconsin, Madison, USA. His current research interests include: VLSI physical design, SOC hardware/software codesign, and Wireless LAN and Bluetooth IC design. Dr. Chen is a member of the Chinese Institute of Engineers, the Chinese Institute of Electrical Engineering, the Institute of Taiwanese IC Design, and a senior member of the IEEE Circuits and Systems and IEEE Computer Societies.