MATHA: Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture

Highlights

• The proposed work consists of four stages, namely selection, analysis, and design and performance comparison.

• First stage – various sense amplifiers are selected for further processing.

• Second stage – selected sense amplifiers (M-DTSA, MCG-DTSA, MDET-DTSA, S-DTSA) are applied with various traffic rates.

• Third stage – reconfigurable DTSA for complete transceiver is designed.

• Fourth stage – performance comparison is made between proposed and conventional approaches.

Abstract

Now-a-days there is much research attempts aim to find out low power consumption in the area of Network-on-chip (NoC), both in architectural as well as algorithmic approach. Even though a lot of Double Tail Sense Amplifiers (DTSA) are used in architectural approach, the conventional DTSA with transceiver exhibits a difficulty of consuming more energy than its indented design during heavy traffic condition. Multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture (MATHA) is designed in this research to eliminate the difficulty. This MATHA is a combination of reconfigurable DTSA and transceiver. The reconfigurable DTSA consist of modified DTSA (M-DTSA), modified clock gating with DTSA (MCG-DTSA), Modified Dual Edge Triggered with DTSA (MDET-DTSA), Soft-DTSA (S-DTSA), graph theory based traffic estimator and multiplexer. Depending upon the traffic rate, one of the DTSA among the available four DTSA is selected and information transferred to the receiver. The proposed MATHA design is evaluated on TSMC 90 nm technology, showing 6.1 GB/s data rate and 0.32 W total link power.

Introduction

Network-on-chip is a booming area for designing current application like multimedia, telecommunication, and real time task [1]. Conventional research mainly focuses on low power, high speed and scalability in networks on chip [2]. Algorithmic [3] and architectural models [4] are made and implemented into the Network-on-chip to provide further performance improvement than existing NoC design. Current Network-on-chip designer’s shows much progress on this architectural level model by introducing external or internal sense amplifier in on chip communication [5]. In addition to transmitter with pre emphasis capacitance for high speed and energy reduction in on chip communication, it requires DC bias circuits at the receiver section. To overcome this issue, voltage sense amplifier is introduced and tested in 90 nm CMOS cross coupled circuit [6]. In small circuit application user cannot identify the worth of voltage sense amplifier so it is refined into Double Tail Sense Amplifier. This DTSA with transceiver consists of pre emphasis capacitance at the transmitter and Double Tail Sense Amplifier at receiver section [7]. A low power consumption model is developed and implemented in many real time applications. Clock gating low power design approach at RTL TSMC 45 nm CMOS application is tested in [8]. CMOS VLSI design has taken us to real working chips that rely on controlled charge recovery to operate at significantly lower power dissipation levels than their existing counterparts. The energy recovering circuits are applied in microcontrollers, memory devices, display drivers, grouped clock networks, and other real time applications [9].

The CG-SAFF (sense-amplifier flip-flop) [10] and DET-SAFF [11] circuit exhibits high speed and low energy, the switching activity and delay of various flip-flops are compared with CG-SAFF and DET-SAFF. Based on synthetic traffic, the performance improvement is achieved in networks with respect to Network traffic modeling [12]. The traffic estimator and generator are introduced for QoS in [13] to generate and estimate the real time traffic data in on chip communication. In this proposed MATHA design, we followed above traffic generator and estimator in traffic model and multiple sense amplifiers. The reconfigurable topology is applied in on chip networks for performance improvement [14], the same methodology is used in the reconfigurable process of this proposed work. Both DET-SAFF and CG-SAFF is refined into modified DET-DTSA (MDET-DTSA) and modified CG-DTSA (MCG-DTSA) and it has been examined under various traffic intensities. To achieve further improvement in DTSA circuitry, we introduce new circuit by adding clock gating and an energy recovery technique [15] called soft DTSA. The goal of this paper is to design multiple sense amplifiers with transceiver for high performance improvement in NoC Architecture (MATHA). The proposed work consists of four stages, namely selection, analysis, and design and performance comparison. In the first stage of our work various sense amplifier selected for further processing and in second stage selected sense amplifiers (M-DTSA, MCG-DTSA, MDET-DTSA, S-DTSA) are applied with various traffic (Data, image, audio, video). In third stage we designed reconfigurable DTSA for complete transceiver. Finally, we compared our results with conventional approaches.

The concept involved in proposed work is shown in Table 1. The rest of this paper is ordered as follows. Section 2 addresses the conventional communication with NoC. Proposed work and its various DTSA details are discussed in Section 3. The proposed experimental results of various architectures are presented in Section 4. Finally, the conclusion is presented in Section 5.