Fig. 1. Overview of 1-D convolution in log-domain.

Fig. 2. An example to demonstrate the concept of log₂ approximation.

Fig. 3. (a) Actual curve and estimated curve of log₂(N) obtained from approximation technique and (b) percentage error of the difference between actual and estimated values.

Fig. 4. Block diagram of 2-D convolution architectures: (a) architecture with explicit pipelining of adder tree and (b) architecture inherently pipelined the adder tree into the leftmost column of PEs.

Fig. 5. Address generator for DPRAMs implementing line buffers.

Fig. 6. Architecture of processing elements.

Fig. 7. (a) Architecture of log₂ and (b) mapping of multiplexers in MBS.

Fig. 8. (a) Architecture of inverse-log₂ and (b) mapping of multiplexers in RMBS.

Fig. 9. Window sliding architecture is used for padding of the borders of the image.

Fig. 10. Edge detection with Laplacian kernel: (a) normalized Laplacian kernel, (b) grayscale input image, (c) 2-D convolution result by Matlab function, (d) 2-D convolution result by hardware simulation and (e) hardware simulation result scaled by 2.

Fig. 11. Plot of error from approximation: (a) difference error between the results of the Matlab double precision function and hardware implementation with Laplacian kernel (average error of 0.17 intensity) and (b) histogram of error with x-axis normalized by peak error at 3.5 intensity.

Fig. 12. Smoothening of image corrupted by Gaussian white noise: (a) grayscale of input image corrupted by Gaussian white noise with m = 0, and σ₂ = 05 , (b) image filtered by Matlab function and (c) image filtered by the proposed hardware.

Fig. 13. Plot of error from approximation: (a) difference error between the results of the Matlab double precision function and hardware implementation with Gaussian smoothening kernel (average error of 0.58 intensity) and (b) histogram of error with x-axis normalized by peak error at 2.59 intensity.

Fig. 14. Combined edge detection and smoothening of images using the proposed hardware with kernel coefficients: (a) scaled by 1 and (b) scaled by 2.

Fig. 15. Timing diagram of log₂ and inverse-log₂ modules.

Performance and hardware utilization of log₂ architecture with various resolutions

Performance and hardware utilization of inverse-log2 architecture with various resolutions

Performance and hardware utilization of PE architecture with various resolutions

Hardware utilization for 8-bit architecture

Comparison of hardware resources and performancewith other 2-D convolution implementations