Abstract

In this paper, the methodology used for prototyping an H.263 basic line video coder is explained. The coder is based on an architecture, which we have called MVIP-2, consisting of a set of specialized processors for the main tasks (transforms, quantizers, motion estimation and motion compensation) and a RISC processor for the scheduling tasks.

The design has been written in synthesizable Verilog and fully tested with hardware–software co-simulation using standard video sequences. All modules except the RISC have been synthesized and fitted onto an FPGA. The prototype has been tested in real-time using a commercial board with the RISC and the FPGA, a pattern generator emulating a video camera to generate the input sequences and a logic analyzer to test the H.263 output stream.

We have used a classic design methodology with some improvements in order to carry out rapid system prototyping. With this improved methodology, a prototype can be obtained early in the design cycle allowing the debugging of some hardware and software components permitting others to be designed at the same time.

In this paper we explain how this methodology has been applied to a complex design (MVIP-2). Despite some details being specific to this design, the main aspects of the methodology can be applied to other designs.

Keywords: H.263; FPGA; RISC; Rapid system prototyping

Article Outline

1. Introduction

2. H.263 video encoding architectures

3. The MVIP-2 architecture

3.1. The MVIP-2 hardware

3.2. The MVIP-2 software

4. Prototyping

4.1. The design methodology

4.2. Improvements for rapid system prototyping

4.3. Design options evaluation using the Verilog testbench

4.4. Design for prototyping

4.5. Configuration for prototyping

4.6. The testbench

4.7. The strategy

5. Results

6. Conclusions

Acknowledgements

References

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