A charge-pump and comparator based power-efficient pipelined ADC technique
Introduction
Pipelined analog-to-digital converters (ADCs) have proved attractive for high-speed and low-power analog-to-digital conversion with medium resolution requirements [1]. They have been widely applied in such areas as wireless communication systems, image processing applications [2], [3], etc., and they have drawn lots of researchers' attention in the literature [4], [5], [6], [7], [8], [9], [10]. In the conventional pipelined ADCs, the accuracy, speed and power limitations mainly stem from the op-amps required for amplifying residue voltages between pipelined stages. High-gain, wide-bandwidth and thus power-hungry op-amps are required for high performance ADCs. Meanwhile, as the feature sizes of transistors in modern CMOS technologies are constantly scaled down, high-gain and high-speed op-amps become more difficult to design and more power-costly due to the declined intrinsic transistor gain and supply voltages [11], [12].
Aiming at overcoming these problems, various pipelined ADC techniques have been proposed in the literature. Some methods optimize the op-amps to minimize the power dissipation, such as the op-amp sharing technique [13], op-amp current reuse technique [14], etc. These techniques have indeed achieved important improvement in power efficiency, yet there are still fundamental limits due to the use of high-gain op-amps in a closed negative feedback loop.
In [15], accurate closed-loop op-amps are replaced by low-gain open-loop amplifiers with amplifier nonlinearity calibrated by digital circuits. Simultaneously, more drastic alternatives have been explored to improve power efficiency by discarding the costly op-amps. In [16], the critical gain stage is constructed by parasitic capacitors and dynamic source-followers, leading to very low power consumption. In [17], the comparator-based circuit is utilized to control the charge transfer and has proved suitable for high-speed high-resolution applications with very high power efficiency [18], [19]. In [20], a capacitive charge-pump based structure is proposed. This technique employs capacitor array and source follower to realize the residue voltage amplification function, achieving significant power reduction while only needing simple gain calibration. In [21], the voltage amplification is built by two proportioned current charge pumps controlled by one comparator. This technique performs ultra-low power consumption for medium-resolution high-speed ADC designs. All the above advanced techniques are significant reformations on improving power efficiency of pipelined ADC.
As an alternative method to avoid power-hungry op-amps, a novel charge-pump/comparator based pipelined ADC is proposed in this paper with low power and reduced design complexity. This technique uses a charge pump to perform the residue voltage amplification and adopts a comparator-controlled charging circuit to buffer the residue voltage to the next stage. The buffer circuit in principle does not sacrifice any voltage headroom, a key advantage over the source follower circuit of [20]. In addition, theoretically the stage gain is larger than that of [20] by departure from using source-follower whose gain never becomes the ideal value of one. This gives chances to minimize the number of stages for targeted resolution and thus saves power consumption.
This paper is organized as follows. Section 2 describes the proposed pipelined ADC technique and the overshoot self-cancellation technique. In Section 3 the power efficiency is analyzed. Circuit implementation is presented in Section 4, followed by the experimental results of the prototype chip in Section 5. Conclusions are given in Section 6.
Section snippets
Conventional 1.5-bit pipelined ADC stage
The 1.5-bit/stage pipelined ADC architecture has been used broadly since its initiation in [22]. Fig. 1 shows a stage in such an ADC. The stage resolves 2 bits with a sub-ADC, and generates a residue voltage Vres to the next stage. With 0.5-bit redundancy, an offset error as large as can be tolerated in the sub-ADC. The sub-DAC, substractor and ×2 gain block, commonly referred to as multiplying digital-to-analog converter (MDAC), play important roles on the performance of the whole ADC.
Power efficiency analysis
In each MDAC stage, the most important task is to charge the capacitors and generate the amplified residue voltage. This operation takes large portion of total ADC power dissipation. In following, we will show that in theory the power consumption of the proposed charging/discharging operation is similar to the dynamic power consumption of a digital circuit. The operation of the second stage in the nth period is used in the analysis, as illustrated in Fig. 5. From the (n−1)th clock period to
Circuit implementation
To verify the proposed concept, a prototype single-ended pipelined ADC was designed in a 0.18 μm CMOS process. Fig. 7 shows the overall block diagram of the ADC. It consists of 10 main “1.5-bit” stages followed by a 2-bit flash in the last stage. The ADC is designed to operate at a speed of 25 MSample/s. Biasing circuit and non-overlapping clock generator are integrated on the same chip. Reference voltages and a reference current are supplied off-chip and the digital calibration is also processed
Measurement results
As a proof-of-concept design, the proposed pipelined ADC was fabricated in a 0.18 μm CMOS process. Fig. 9 displays the die photograph, which occupies an active area of 0.39 mm2. Since the design is pad-limited, the lower part of the chip is filled up with decoupling capacitors composed of MOSFET.
The gain calibration is performed off-line, showing a gain of 2 in 1st stage, and gains of round 1.5 in the 2nd to 10th stages. The lower-than-expected gain of 1.5 in later stages is mainly caused by the
Conclusions
In this paper the charge-pump/comparator-based power-efficient pipelined ADC technique has been introduced. The proposed technique saves power in the most critical block of residue voltage amplification by using a passive charge pump with a buffer implemented by a comparator-controlled charging circuit. The proposed circuit in principle has a greater signal range than the traditional charge pump followed by a source follower. The proposed technique also allows the use of simple digital
Acknowledgment
The work described in this paper was supported equally by two Grants from the Research Grants Council of the Hong Kong Special Administrative Region, China (Project no. CUHK 416409 and CUHK 416011).
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