CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs
Introduction
With the advent of deep submicron technologies, interconnections are becoming the dominant aspect of the circuit delay for state-of-the-art circuits, and this fact is becoming more significant at each new technology generation [1]. This is due to the fact that gate speed, density and power scale are obeying Moore's law, while the interconnection resistance–capacitance product increases with each technology node, with a consequent increase in the network delay [2], [3]. In field programmable gate arrays (FPGAs), interconnections play an even more crucial role, because they not only dominate the delay [4], but they also severely impact power consumption [5] and area [6]. For million-gates FPGAs, as much as 90% of the chip area is devoted to interconnections [7].
Multiple-valued logic (MVL) targeted to FPGAs was already shown in [8], [9], [10]. Most efforts to accomplish multiple-valued FPGAs have presented current-mode circuits or hybrid implementations of CMOS and quantum devices to be used in configurable logic blocks (CLB). These circuits present successful improvements in reducing area, but their excessive static power consumption and realization complexities have precluded their acceptance as a viable alternative to standard CMOS designs.
In order to deal with the static power dissipation problem using a standard CMOS process, and still maintain the logic compaction allowed by MVL, this paper presents a new methodology that uses quaternary look-up tables implemented using voltage-mode CMOS logic. The look-up table circuit presented is a transmission gate (T-gate) like circuit that uses down literal circuits, binary inverters and pass transistor gates.
To cope with interconnections costs, we propose the use of multiple-valued logic to compact information, since a single wire can transmit more than two distinct signal levels. This can lead to a reduction on the total interconnection costs, hence reducing area, power and delay, what is especially important in FPGA designs.
In order to evaluate the proposed technique, this paper presents simulations of quaternary LUTs of 1, 2 and 3 quaternary control inputs, and compares them to their corresponding binary LUTs, the basic logic block used in several commercial FPGAs. Circuits are simulated with the SPICE tool using TSMC 0.18 μm technology. Logic mapping of quaternary functions into look-up tables is shown for a set of functions to emulate the use of such circuits in the configurable logic block of an FPGA.
Section snippets
Binary and quaternary look-up tables
Field programmable gate arrays are two dimensional arrays of logic blocks and flip-flops with electrically programmable interconnections among those. In several modern FPGAs, look-up tables are used as logic blocks to implement any number of different functionalities. The desired function input feeds the input signals of look-up tables. The output of the look-up table gives the result of the logic function that it implements. In digital logic, an n-bit look-up table can be implemented with a
Quaternary LUT design
The proposed QLUT is based on a voltage-mode quaternary logic CMOS circuits presented in a previous work [16]. This new family of circuits uses several different transistors with different threshold voltages, and operates with four voltage levels, corresponding to logic levels ‘0’, ‘1’, ‘2’and ‘3’. The QLUT presented in this work is designed using down literal circuits (DLCs), binary inverters and pass transistor gates. There are three possible down literal circuits in quaternary logic [17],
Simulation results
Simulations of look-up table circuits were carried out with the Spice tool using TSMC 0.18 μm technology. In this work we present results for binary 2LUT, 4LUT and 6LUT and quaternary QLUT, 2QLUT and 3QLUT to estimate and compare their power consumptions, area and performance.
Circuits were simulated for all possible transitions of the control inputs. As an example, Fig. 5 shows the output transients of the QLUT mapping the quaternary inversion function, i.e., for ‘0’, ‘1’, ‘2’ and ‘3’ at the
Logic mapping
Using only quaternary look-up tables as logic elements, several quaternary functions were simulated by mapping their truth tables into a set of QLUTs by correctly settings all inputs and interconnections. A logic mapping was also performed for the binary correspondent function using binary look-up tables, with the ABC logic minimization software [18].
Our benchmark set is composed of the functions named sum3, sum4, sum5, sum6, sum22 and prod22, which are summation of 3, 4, 5 and 6 quaternary
Discussions
Simulation results affirm the functionality of the developed quaternary logic circuits, and also show that these circuits can achieve a satisfactory performance and excellent improvements in area and power consumption. Moreover, it is worth to emphasize that the major gain with the use of quaternary logic instead of binary logic is the ability to compact more information in a single gate or wire, which favors the cost reduction in the interconnect network, since the amount of wires can be
Conclusion
This work presented some steps towards a low-power, reduced area quaternary FPGA. We presented low-power quaternary look-up tables intended to be used in configurable logic block for high density FPGA designs. Simulation results showed a reduction of the LUT area and power consumption compared to binary equivalent LUTs. Logic mapping of quaternary functions into quaternary LUTs showed high improvement in overall characteristics compared to binary equivalent mapping. Results also showed a clear
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