Novel attributes in scaling issues of carbon nanotube field-effect transistors
Introduction
With the end of silicon transistor scaling, carbon nanotubes (CNTs) are at the forefront of current research as a promising alternative to the conventional silicon technology [1] for future nanoelectronics at the end of the International Technology Roadmap for Semiconductors (ITRS) [2]. They are particularly attractive for high-speed applications due to their quasi-ballistic properties [3], [4] and high Fermi velocity (∼106 m/s) [5]. It has been shown experimentally that the current in semiconducting CNTs can be controlled by external fields, and CNT field-effect transistors (CNTFETs) have been demonstrated [6]. CNTFETs are ultra thin body devices [7] that do not suffer from severe mobility degradation as typically observed for silicon MOSFETs with nanometer dimensions [8]. CNT transistors scaled down to ∼10 nm or even shorter have attracted a great deal of interest [9], [10]. Experiments have shown that CNTFETs have excellent electrical properties, including high transconductance, high on/off-current ratio, extraordinary mobility and almost ballistic transport in CNT devices [11], [12].
Rapid progress in the field has recently made it possible to fabricate digital and analogue CNTFET-bases circuits, such as logic gates, static memory cells and ring oscillators [13], [14].
With the intrinsic advantages of CNTs established, the main question to address is What device geometry is ideally suited to enable optimum device performance? How do we make best use of the intrinsic potential of CNTs as three-terminal devices? In this paper, we will discuss the role of CNT diameter and gate oxide thickness on the performance of CNTFETs over wide range using a two-dimensional (2-D) simulation. Because to explore the role of CNTFETs in future integrated circuits, it is important to evaluate their performance and the nanotube diameter and gate oxide thickness have direct relevance for the electrostatic control in a CNTFET. The unique features of the CNTFET device with different CNT diameters and gate oxide thicknesses are explored in terms of transfer characteristics, output characteristics, average velocity, transconductance, drain conductance, voltage gain, Ion/Ioff ratio, drain-induced barrier lowering (DIBL) and subthreshold swing with a purpose of uncovering the potential benefits by their possible integration in current VLSI technology.
Section snippets
Two-dimensional model
At low gate voltages, the energy barrier between the source and drain is high, and the device is off. A high drain bias lowers the energy in the drain, and when a high gate voltage lowers the potential energy barrier, electrons flow from source to drain. With respect to that the top of the energy barrier between the source and drain has special significance in operation of FETs. Therefore, it can be the good starting point for a model. Our key task in developing model will be to devise a simple
Results and discussion
A schematic structure of a coaxially gated n-type CNTFET is shown in Fig. 2. The coaxial gate geometry offers the best electrostatic gate control. The intrinsic nanotube channel is separated from the source/drain metal contact by the heavily n-doped nanotube source/drain extension to minimize the Miller capacitance between gate and source/drain electrode. The source/drain region could also be realized by using weakly coupled metal–nanotube contacts with an appropriate metal work function [18].
Conclusion
In this paper, novel attributes of scaling issues on the performance of CNTFETs has been studied using 2-D model. It is found that using thinner gate oxide and larger CNT diameter in CNTFETs are caused by the enhancement in average electron velocity at the top of the barrier, on-state current, transconductance, output conductance and voltage gain. In addition, off-state current, DIBL and subthreshold swing improve in CNTFETs with thinner gate oxide, but they become worse in CNTFETs with larger
References (23)
- et al.
Investigation of the novel attributes of a carbon nanotube FET with high-κ gate dielectrics
Physica E: Low-dimensional Syst. Nanostructures
(2008) - et al.
Carbon nanotube field-effect transistors for logic applications
IEDM Tech. Dig.
(2001) - The International Technology Roadmap for Semiconductor 2006 Update, ITRS Handbook, Online, available at:...
- et al.
Lateral scaling in carbon nanotube field-effect transistors
Phys. Rev. Lett.
(2003) - et al.
Electron–phonon scattering in metallic single-walled carbon nanotubes
Nano Lett.
(2004) - et al.
Fabry–Perot interference in a nanotube electron waveguide
Nature
(2001) - et al.
Logic circuits with carbon nanotube transistors
Science
(2001) - et al.
Self-aligned carbon nanotube transistors with charge transfer doping
Appl. Phys. Lett.
(2005) - et al.
Performance of carbon nanotube field effect transistors with doped source and drain extensions and arbitrary geometry
IEDM Tech. Dig.
(2005) - et al.
Performance projections for ballistic carbon nanotube field-effect transistors
Appl. Phys. Lett.
(2002)