Study of asymmetrical effects of silicon submicron transistors
Introduction
Metal oxide semiconductor field effect transistor (MOSFET) is the most important fundamental device for ultra large scale integrated circuits [1]. New advanced technology with smaller channel length transistor is coming to the market in every few years. The effect of channel length on asymmetrical of drain and source become important and imperative to study [2], [3], [4], [5], [6].
The objective of this work is to study the effect of asymmetry of drain and source of silicon MOS transistor with different submicron channel lengths over the wafer. This work is divided into two parts. The first part is focused on threshold voltage measurement with transconductance extraction and constant-current (CC) methods for different channel length MOS transistors, such as 0.18, 0.13 and 0.09 μm. In the transconductance (gm) extraction method, the threshold voltage is determined by extrapolating the gm(=dIds/dVg)−Vg relation in the low ON current region as shown in Fig. 1. The typical drain current Id,gm versus gate voltage Vg curve that was used to determine the threshold voltage Vto by gm extraction method. The constant current method is obtained by measuring the gate voltage at which a specific small drain current (=0.1 μA) flows at source–drain bias Vds=0.1 V and this gate voltage is defined as threshold voltage Vtlin.
The effective channel length (Leff) was determined by using ‘shift and ratio’ methods instead of conventional channel resistance methods. It is found that the standard deviation of threshold voltages and effective channel length were increased with decrease of transistor channel length.
Section snippets
Experimental
The silicon MOS transistors were fabricated in the eight inch size wafer by Chartered Semiconductor Manufacturing Company. The NMOS transistor used in this experiment were a retrograded twin well implant. The COSi2 was used for shallow trench isolation (STI) to reduce the series resistance. Three different channel lengths of 0.18, 0.13 and 0.09 μm transistors were used for this investigation. The intermediate type channel width (W=0.3 μm) transistors were mainly used for this investigation. For
Results and discussions
The typical I–V characteristic curves of drain current (Id) versus gate voltage (Vg) are shown in Fig. 2 for channel length 0.18, 0.13 and 0.09 μm NMOS transistors. Each transistor was measured twice by swapping the drain and source bias voltage. The threshold voltage (Vto) decreased as the channel length (L) decreased from 0.18 to 0.09 μm. There are supposed to be a ‘roll-up’ then followed by a ‘roll-off’ effect of reverse short channel effect (RSCE) in the threshold voltage of transistor [3],
Conclusion
The effect of channel length on asymmetrical of drain and source were investigated. The standard deviation of threshold voltages Vto and Vtlin are increased for advanced technologies as channel length becomes smaller. The asymmetry of drain and source is increased for the shorter channel transistor. Moreover, due to the ‘rounding off errors’ limitation in Vtlin measurement, statistical variation of Vto shows the higher confidence level than Vtlin. Effective channel length (Leff) was determined
Acknowledgements
The authors would like to acknowledge Chartered Semiconductor Manufacturing (CSM) for supplying wafers with devices. We would also like to thanks Dr Lap Chan and Mr Tee Kheng Chok, CSM for their help in this work.
References (9)
- et al.
Comparison of MOSFET-threshold-voltage extraction methods
Solid-State Electron.
(2001) Sillicon Processing
(1995)- et al.
Physically-based threshold voltage determination for MOSFET's of all gate lengths
IEEE Trans. Electron. Devices
(1999) - et al.
New method for extraction of MOSFET parameters
IEEE Electron. Device Lett.
(2001)