Moore’s crystal ball: Device physics and technology past the 15 nm generation
Graphical abstract
Introduction
For the past 40 years, relentless focus on Moore’s Law transistor scaling has provided ever-increasing transistor performance and density. An excellent example is provided by SRAM scaling over the last five generations, where steady adherence to Moore’s Law has delivered 2X bitcell area scaling each generation (see Fig. 1).
As we look forward to the 15 nm node and beyond, there are a number of critical challenges to be addressed. These challenges include reducing the effective gate length (Leff), reducing the gate pitch, and targeting the threshold voltage (VT).
Reducing Leff is a critical challenge for advanced technology generations. Increased off-state current (Ioff) from degraded drain-induced barrier lowering (DIBL) and subthreshold slope (SS) caused by poorer short channel effects (SCE) represents a significant limitation for Leff shorter than approximately 15 nm. Decreasing the gate oxide thickness (Tox) to provide better channel control comes with a penalty of increased gate leakage current (Igate) and increased channel doping (to increase threshold voltage, VT) to maintain Ioff. Increased channel doping decreases mobility (degrading performance due to impurity scattering), as well as increasing random dopant fluctuations (RDF). Increasing RDF increases variation in VT with subsequent impact to the minimum operating voltage (Vmin).
Reducing gate pitch is also a critical challenge for advanced technology generations. Decreasing gate pitch decreases the stress enhancement for both NMOS (stress induced by overlayer films) and PMOS (stress induced by embedded-SiGe, e-SiGe) thus decreasing mobility and drive. Decreasing gate pitch increases the parasitic capacitance contribution for both contact-to-gate and epi-to-gate thus increasing overall gate capacitance (Cgs). Finally, decreasing the source/drain opening size increases the source drain resistance (Rsd) thus decreasing drive current.
Targeting VT is a critical challenge for advanced technology generations, particularly for the low power system-on-chip (SOC) processes. The critical conflict is between the need for higher VT (to produce lower Ioff and reduce stand-by power) and the need for lower VT (to produce lower Vmin and reduce active power).
Section snippets
Improving electrostatic confinement
Maintaining the scaling roadmap will require continual improvement in short channel properties. A variety of device architectures which improve electrostatic confinement (and thus short channel control) are being investigated for advanced technology nodes. These architectures can be broadly categorized by the method of electrostatic confinement. There are architectures which provide additional electrostatic confinement with a planar architecture (ultra-thin body (UTB), fully-depleted SOI
Mobility enhancements
Maintaining the scaling roadmap will require continual improvement in channel mobility. Short term approaches include reorienting the surface or channel of the device, and implementing improved strain techniques. Long term solutions may include more exotic channel materials (Ge, III–V, etc.).
Resistance and next generation transistors
Improving the traditional resistive elements, such as the accumulation (Racc), spreading, silicide and contact resistances, will become more challenging at the reduced dimensions of advanced technologies. Furthermore, resistance elements previously neglected (including interface and epi resistance) are becoming significant issues. Moreover, the various non-planar architectures will introduce new resistance components associated with small dimension fins and wires.
All these resistive components
Capacitance and next generation transistors
Improving the traditional capacitance elements, such as under-lap capacitance (Cxud), channel capacitance, junction capacitances (both gated edge and area) and the inner and outer fringe capacitance; will become more challenging at the reduced dimensions of advanced technologies. Furthermore, in recent generations, gate and contact critical dimensions have been scaling slower than contacted gate pitch. This means that parasitic fringe capacitances (for example, contact-to-gate and epi-to-gate)
Conclusions and summary
While significant transistor challenges (SCE, resistance, capacitance, mobility, etc.) exist for technologies past 15 nm, numerous solutions are being explored to drive Moore’s Law forward. Advanced junction engineering will play a critical role in the transistor roadmap past 15 nm.
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