Fabrication and electrical performance of high-density arrays of nanometric silicon tips
Introduction
Silicon tips are very interesting structures that can be used for fabrication of Field Emission Devices (FED) [1], [2], [3], [4] such as Flat Panel Displays (FPD) [1], [2], [3], microwave power tubes [1], [2], pressure sensors [1], [2], [5], [6] and electron source for X-ray devices [7]. There are also other types of applications that are not based in electron emission as for example tips for scanning microscopy [8], [9], MEMS [10], [11], biomedical applications [12], [13] or antireflection coatings on silicon [11], [14].
For Field Emission applications the radius of curvature of the tip and the array density [1], [15] are important parameters for determining the efficiency of the device. Thus the lithography is one of the most important features in the manufacturing of FEDs. The optical lithography is the simplest and less-expensive lithographic technique, but its low resolution limits the size of the tip as well as the density of the arrays. Although nowadays, deep UV steppers allow the lithography of structures up to 100 nm [16], such systems are very expensive or dedicated to certain processes in microelectronic industry. Focused Ion Beam (FIB) or E-beam systems are multipurpose equipments that achieved high resolution; however, the sequential nature of these recording processes requires long time to perform large areas, resulting also in high costs. Thus the Interference Lithography (IL) is a cheaper alternative to record submicrometric periodic patterns in large areas [17], [18], [19]. Although the IL has been already proposed [17] to record photoresist periodic patterns for manufacturing of Field Emission Tips, the complete manufacturing of the tip arrays using IL never has been demonstrated neither measured the emitting ability of the tips.
The problem for using IL is the low contrast of the sinusoidal fringe pattern that make difficult the recording of high aspect ratio photoresist structures. Besides this fact IL is not a usual process in the manufacturing of semiconductor devices. In addition, the use of high coherent light sources, required to create the interference patterns, increases very much the contrast of the Standing Waves (SW) [20], [21] pattern generated by the reflection on the Si substrates, requiring the use of antireflection coatings (AR) [18], [20], [22], [23].
In this paper we propose and demonstrate a few steps process, fully compatible with the Si technologies, that associates Interference Lithography and the isotropic RIE for recording Field Emission Silicon tips.
Section snippets
The tips fabrication process
In general, two types of process are used for the fabrication of tips arrays: the Spindt-type process and the Silicon tip-on post process. The Spindt-type process is used for fabrication of metallic tips by deposition or evaporation [1], [2], [24], [25] and the Interference Lithography may be used to define the gate pattern. Many applications, however, require the fabrication of silicon tips for integration in microelectronics devices. Thus in the silicon tip-on-post type process [1], [2], [19]
Electrical performance
The fabricated high-density array of silicon nanotips, showed in the Fig. 5b, was operated as a field electron emission device for the characterization of the current–voltage dependence and the temporal stability of the electron current.
Structures with small radius of curvature, as the tips, induce the concentration of the electric field lines that produces an intense field around the tip. If a voltage Vg is applied between the tip and the anode, which are distanced of τ, the electric field
Conclusions
We demonstrated a simple and low cost process for manufacturing of Field Emission Si tips using Interference Lithography and isotropic Reactive Ion Etching. In particular, the use of proper thickness of SiO2 avoids the use of BARC as well as it can be used as a selective mask for etching the Si, reducing the steps of the RIE and using materials fully compatible with the silicon technologies. The obtained silicon tips have curvature radius of about 20 nm on the top and height of about 1 μm,
Acknowledgments
We are thankful to the financial support given by FAPESP, FAPEMIG and CNPq.
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