Characterization and impact of reduced copper plating overburden on 45 nm interconnect performances
Introduction
For sub-micronic dimensions, copper interconnects properties are dramatically modified with technological downscaling. Dimensions of the thinnest copper wires are close to the electron mean free path and electrical resistivity of interconnects increases due to scattering effects on sidewalls and grain boundaries [1]. Reliability of interconnects is higly impacted, mainly due to electromigration phenomenon [2]. Previously [3], we introduced a modification into the 65 nm damascene process in order to modify copper recrystallization behaviour between electrochemical deposition (ECD) and chemical–mechanical polishing (CMP) steps. Morphological modifications induced by the reduction of the sacrificial overburden thickness using a pre-CMP step was observed after annealing using FIB microscopy. These results were in agreement with the simulations of Jung et al. previously reported [4]. FIB microscopy revealed a stabilized microstructure of copper along and in depth of 90 nm width wires for 200 and 100 nm overburden thicknesses. Copper microstructure inside wires was found bamboo-like before subsequent annealing.
In this study, we modified the overburden (OB) thickness and thermal treatment for blankets films and for 45 nm node patterned samples in order to reproduce previous 65 nm results. Electrical performances were monitored using standard parametrics measurements and RC delay variations are presented for three hot-plate annealing temperatures and modified overburden. Impact of OB reduction on interconnect reliability is then discussed.
Section snippets
Films modified by polishing
Overburden due to ECD over-deposition is a sacrificial film removed during CMP. Reducing the film thickness before stabilization annealing was achieved with CMP Real-Time Profile Control (RTPC) [5], originally introduced for Cu bulk polishing pressures adjustment on Applied Material CMP tool. Thickness was monitored across 300 mm wafers during polishing. The uniformity after partial CMP step is well controlled, as shown in Fig. 1, for thicknesses down to 100 nm.
In a first part, we prepared
Patterned samples observations
In a second part, OB observations over line structures were performed with FIB microscopy, based on crystallographic imaging contrasts [6]. Two types of serpentines lines (1.0/5.6 and 0.07/0.07 μm width/space) with standard 550 and 100 nm modified OB are presented in Fig. 4. For the reference sample (first pictures line), no morphological differences are observed in overburden for both kinds of structure. For the thin OB (second and third picture lines), morphological variations are observed. OB
Electrical and reliability results
Combs and serpentines were electrically tested after complete Back-End integration and final anneal. Four wafers per batch were identically processed. Yield is preserved in all case and no significant difference was observed according to overburden thickness variations for samples annealed, especially at reference temperature. Fig. 6 presents the RC delay modifications induced for reference sample and 200 nm modified overburdens. Anneal temperature effect is observed when reducing overburden and
Conclusion
CMP modified copper films and electroplated overburden were studied. Real-Time Profile Control used during partial polishing allows the realization of films down to 100 nm with reproducibility, even for a nonstabilized ECD copper microstructure. As discussed in paragraphs 2 and 3, films or overburden thickness reduction induced a difficulty to recrystallize copper for low temperature (180 °C) during short (90 s) annealing. However, for patterned samples, copper grain growth occurs differently over
Acknowledgements
The authors gratefully acknowledge STMicroelectronics teams for help in samples preparation. The authors thank the European Project IST-Pullnano and the French ANR project CRISTAL for supporting this work.
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