doi:10.1016/j.mee.2006.11.012
Copyright © 2006 Elsevier B.V. All rights reserved.
The meta-stable dip (MSD) effect in SOI FinFETs
Jang-Gn Yuna, Maryline Bawedinb, c, Sorin Cristoloveanub, Denis Flandrec and Hi-Deok Leea,
, 
aDepartment of Electronics Engineering, Chungnam National University, Yuseong, Daejeon 305-764, Republic of Korea
bInstitute of Microelectronics, Electromagnetism and Photonics, ENSERG, B.P. 257, 38016 Grenoble Cedex, France
cMicroelectronics Laboratory, Université Catholique de Louvain (UCL), Place de Levant 3, B-1348 Louvain-La-Neuve, Belgium
Received 10 August 2006;
revised 31 October 2006;
accepted 30 November 2006.
Available online 9 January 2007.
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Abstract
The meta-stable dip (MSD) effect is demonstrated and characterized in SOI FinFETs. With ascending scan of front-gate voltage (VG1), the magnitude of drain current (ID) tends to be fixed within a specific region of the front-gate voltage and this leads to a dip of transconductance (gm). The dip width can be modulated through a control of bias condition or measurement speed such as back-gate voltage (VG2), drain voltage (VD) and step size of the front-gate voltage. From the dual-gate transient measurement, it is found that the MSD effect is highly dependent on the floating-body effect. In SOI FinFETs, the MSD effect is significantly affected by the fin width due to the fringing electric field of the lateral gates.
Keywords: MSD effect; Floating-body effect; Transient effect; SOI; FinFETs
Fig. 1. (a) Transconductance and (b) drain current characteristics in N-channel FinFET with ascending scan of the front-gate voltage (W/L = 10/10 μm/μm, VD = 0.1 V). Similar characteristics are measured for short devices.
Fig. 2. The influence of (a) drain voltage and (b) step size of front-gate voltage on the MSD window (W/L = 10/1.2 μm/μm, VG2 = 7 V).
Fig. 3. Dual-gate transient measurements by triggering the front- and back-gate voltages at time = 0 s with different (a) back-gate voltages (at VG1 = −2 V) and (b) front-gate voltages (at VG2 = 10 V) (W/L = 10/1.2 μm/μm, VD = 0.1 V).
Fig. 4. The transconductance characteristic in FinFET devices with different fin width at high back-gate voltage (L = 10 μm, VG2 = 10 V, VD = 0.1 V).