Abstract

As the line rates standards are changing frequently to provide higher bit rates, the routers design has become very challenging due to the need for new wire-speed router's network processor (NP) unit. Typically, designing new NPs could take a long time and is very costly. In this work, we are presenting a new approach in high-speed routers design. Our approach is to use a data stream distributor (or DSD) to split the high bit rate line to few lower rate lines. These low rate lines will be processed by existing NPs that are already in use with today routers that are designed to support such low line rates. Such approach will allow the developing of routers in a short time and at a low cost. Clearly, there are many design challenges associated with this approach of routers design such as load balancing, buffer managing, and traffic distribution.

This paper discusses the concept, advantages, and the architecture of the DSD approach. Also, we highlight the implementation of the DSD chip design using a Virtex Xilinx System-On-Chip (SOC) and specifically the Virtex XCV 150 chip. The cycle's accurate simulation has shown that the designed DSD chip is capable of splitting a 2.5 Gb/s line rate to four low bit rate lines of 622 Mb/s. The chip has 118,065 gates and runs at 70 MHz.

Keywords: Router architecture; Network processor; FPGA; Cycle accurate simulation

Article Outline

1. Introduction

2. Processing challenges and related work

3. The parallel network processors design

4. DSD design challenges

5. General description of the DSD

6. DSD architecture and load balancing

7. DSD Implementation

8. Conclusions

References