Low thermal budget selective epitaxial growth for formation of elevated source/drain MOS transistors
Introduction
The continued miniaturization in size of large-scale integrated (LSI) devices has created the need for a shallow junction source/drain (S/D) structure to minimize the short-channel effect [1]. An elevated source/drain (ESD) metal oxide semiconductor field effect transistor (MOS-FET) structure is one of the most promising candidates for improving electrical performance. We have fabricated an ESD structure by means of a selective epitaxial growth (SEG) technique using ultrahigh vacuum chemical vapor deposition (UHV-CVD) [2], [3], [4]. The UHV-CVD method enables the growth of a selective epitaxial growth silicon (SEG-Si) layer at temperatures below 700°C. In the normal UHV-CVD procedure, in situ preheating, typically above 700°C, is carried out to remove native oxide or hydrocarbon contamination on the surface before performing epitaxial growth [2], [3], [4]. However, preheating at a higher temperature induces the diffusion of dopants in the Si substrate. Therefore, it is necessary to lower the preheating temperature to perform a low thermal UHV-CVD process for the fabrication of LSI devices.
The SEG process can be influenced by various treatments performed before the UHV-CVD process, such as dry etching, ion implantation, thermal treatments, etc. In particular, the etching process used for the fabrication of sidewalls, which are arranged beside a gate electrode, forms a damaged layer on the S/D surface. This damaged layer prevents any lowering of the preheating temperature [5]. In our previous report [6], it was shown that the etching conditions, such as the etching gases or overetching steps used to form the sidewalls, influence the SEG-Si morphology. In this study, we investigated how etching conditions affected the morphology of SEG-Si and consequently optimized the conditions of both the etching process and the SEG process to fabricate a morphologically flat SEG-Si surface without the need for higher temperature preheating.
Section snippets
Experiment
Fig. 1 shows the four steps of the experimental procedure used in this study: gate electrode formation, doping in the MOS region, sidewall formation, and epitaxial Si growth on the S/D region. p-type Si(1 0 0) wafers (8–12 Ω cm) were prepared. The gate electrodes were formed first. After the area without MOS regions was masked by optical resist (by lithography), the MOS regions were dosed with As ions by ion implantation: the dosage and the acceleration energy were 4.0×1014 ions/cm2 and 10 kV,
Dependence of morphology of Si epitaxial film on the etching conditions
Fig. 2 shows (1 1 0) cleaved cross-sectional scanning electron microscopy (SEM) images of grown Si adjacent to the gate electrodes of the MOS regions. After the sidewalls were formed by etching with (a) CHF3/Ar plasma or (b) Cl2 plasma using a 10% overetching step, the wafers were loaded into the UHV-CVD apparatus to grow the SEG-Si at 650°C for 20 min without preheating, during which the Si2H6 and the Cl2 flow rates were 1.5 and 0.05 sccm, respectively. The resulting surface morphologies were
Conclusion
We examined the morphology of selective epitaxially grown Si on actual MOS devices with Si3N4 sidewalls by using ultrahigh vacuum chemical vapor deposition (UHV-CVD) without higher temperature preheating. We confirmed that the morphology of the selective epitaxially grown silicon (SEG-Si) is strongly dependent on the dry etching conditions used for the formation of the sidewall structures. We also found that the formation of sidewalls with chlorine (Cl2) plasma is a suitable method to form an
Acknowledgments
The authors would like to thank K. Yamamoto and T. Inagaki for their helpful discussions.
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