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Electronic Notes in Theoretical Computer Science
Volume 200, Issue 1, 25 February 2008, Pages 33-50
Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design (FMGALS 2007)
 
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Copyright © 2008 Elsevier B.V. All rights reserved.

Dataflow Architectures for GALS

Syed Suhaiba, Deepak Mathaikuttya and Sandeep Shuklaa

aFERMAT LAB, Bradley Department of Electrical and Computer Engineering, Virginia Tech, Blacksburg, USA


Available online 23 February 2008.

Abstract

In Kahn process network (KPN), the processes (nodes) communicate by unbounded unidirectional FIFO channels (arcs), with the property of non-blocking writes and blocking reads on the channels. KPN provides a semantic model of computation, where a computation can be expressed as a set of asynchronously communicating processes. However, the unbounded FIFO based asynchrony is not realizable in practice and hence requires refinement in real hardware. In this work, we start with KPN as the model of computation for GALS, and discuss how different GALS architectures can be realized. We borrow some ideas from existing dataflow architectures for our GALS designs.

Keywords: Kahn process networks; globally asynchronous locally synchronous; unbounded FIFO channels

References

M. Bohr. Interconnect scaling – The real limiter to high performance VLSI. In IEEE Int. Electron Devices Meeting, pages 241–244, 1995.

E. Lee and A. Sangiovanni-Vincentelli, A framework for comparing models of computation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17 (12) (1998), pp. 1217–1229. View Record in Scopus | Cited By in Scopus (129)

J. Dennis. First version of a data flow procedure language. In G. Goos and J. Hartmanis, editors, Proceedings of the Programming Symposium. Springer-Verlag, 1974.

Arvind and R. Nikhil, Executing a program on the mit tagged-token dataflow architecture, IEEE Transactions on Computers 39 (3) (March 1990), pp. 300–318.

L. Carloni and A. Sangiovanni-Vincentelli, Coping with latency in SoC design, IEEE Micro, Special Issue on Systems on Chip 22 (5) (October 2002), p. 12.

L. Carloni, K. McMillan and A. Sangiovanni-Vincentelli, Theory of latency-insensitive design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 (9) (2001), pp. 1059–1076. View Record in Scopus | Cited By in Scopus (84)

J. Cortadella, M. Kishinevsky, and B. Grundmann. Synthesis of synchronous elastic architectures. In Proceedings of the 43rd annual conference on Design automation, pages 657–662. ACM Press New York, NY, USA, 2006.

S. Suhaib, D. Mathaikutty, D. Berner and S. Shukla, Validating families of latency insensitive protocols, IEEE Transactions on Computers 55 (11) (2006), pp. 1391–1401. View Record in Scopus | Cited By in Scopus (5)

T. Grotker, System Design with SystemC, Kluwer Academic Publishers Norwell, MA, USA (2002).

A. Gerstlauer, System Design: A Practical Guide with SpecC, Kluwer Academic Publishers (2001).

W. Acherman and J. Dennis. Val-Oriented Algorithmic Language, Preliminary Reference Manual. Technical Report MIT-LCS-TR-218, MIT, 1979.

A. Davis. The architecture and system method of DDM1: A recursively structured Data Driven Machine. In Proceedings of the 5th annual symposium on Computer architecture, pages 210–215. ACM Press New York, NY, USA, 1978.

T. Chelcea and S. Nowick, Robust interfaces for mixed-timing systems, IEEE Transactions on VLSI 12 (8) (Aug 2004), pp. 857–873.

L. Carloni, The Role of Back-Pressure in Implementing Latency-Insensitive Systems, Electronic Notes in Theoretical Computer Science 146 (2006), pp. 61–80. Abstract | PDF (344 K) | View Record in Scopus | Cited By in Scopus (3)

D. Kim, M. Kim, and G. Sobelman. Asynchronous FIFO Interfaces for GALS On-Chip Switched Networks. In International SoC Design Conference, 2005.


Electronic Notes in Theoretical Computer Science
Volume 200, Issue 1, 25 February 2008, Pages 33-50
Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design (FMGALS 2007)
 
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