Copyright © 2005 Elsevier B.V. All rights reserved.
On the Transformation of SystemC to AsmL Using Abstract Interpretation
Available online 18 May 2005.
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Abstract
SystemC is among a group of system level design languages proposed to raise the abstraction level for embedded system design and verification. A straight and sound verification by model checking or theorem proving of SystemC designs is, however, infeasible given the object-oriented nature of this library and the complexity of its simulation environment. We illustrated, in a previous work, the feasibility and success of performing model checking and assertions monitors generation of SystemC using a variant of Abstract State Machines (ASM) languages (AsmL). In this paper, we establish the soundness of our approach by proving the correctness of the transformation from SystemC to AsmL.
Keywords: SystemC; Formal Verification; Abstract Interpretation






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