Copyright © 2007 Published by Elsevier B.V.
Memory management optimization problems for integrated circuit simulators
Received 30 September 2004;
Abstract
In hardware design, it is necessary to simulate the anticipated behavior of the integrated circuit before it is actually cast in silicon. As simulation procedures are long due to the great number of tests to be performed, optimization of the simulation code is of prime importance. This paper describes two mathematical models for the minimization of the memory access times for a cycle-based simulator.
An integrated circuit being viewed as a directed acyclic graph, the problem consists in building a graph order on the vertices, compatible with the relation order induced by the graph, in order to minimize a cost function that represents the memory access time. For both proposed cost functions, we show that the corresponding problems are NP-complete. However, we show that the special cases where the graphs are in-trees or out-trees can be solved in polynomial time.
Keywords: Graph ordering; Integrated circuit simulation; Complexity
Article Outline
- 1. Introduction
- 2. Models
- 2.1. Directed sum cut
- 2.2. Uniform cost stack
- 2.3. Remarks
- 3. The DSC model
- 3.1. Complexity
- 3.2. Polynomial cases
- 4. The UCS model
- 5. Conclusion
- References






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