Dynamic partial reconfigurable Viterbi decoder for wireless standards☆
Graphical abstract
Highlights
► A high speed, low power dynamically reconfigurable Viterbi decoder is proposed. ► An improved modular design of Add Compare Select (ACS) and Trace back units reduces critical path delay. ► With a throughput of 81 Mbps, the proposed architecture is suitable for 802.11a, CDMA, UMTS and EDGE. ► An application of dynamic partial reconfiguration reduces area and configuration time.
Introduction
Convolution codes, which allow for efficient hard-decision decoding, and the Viterbi algorithm [1] are known to provide a strong forward error correction (FEC) scheme, which has been widely utilized in digital communication applications. There has been a growing need for devices that have the flexibility to support multiple communication standards. A reconfigurable architecture, which has the flexibility to operate in multiple standards, has obvious advantage over conventional devices in terms of smaller area and seamless switching across standards [5]. Each wireless standard specifies a different constraint length which imparts different requirement on the Viterbi decoder. General Packet Radio Service (GPRS) uses a constraint length 5 and rate 1/2 decoder. Enhanced Data for Global Evolution (EDGE) uses a constraint length 7 and rate 1/3 decoder. Wi-Fi and WiMAX make use of constraint length 7 [11]. The rapid growth of wireless communications has led to the demand for communication devices which can support multi-standards and have the capability of switching from one to another on the fly [3], [5].
There are many architectures of Viterbi decoder in the literature [2], [10], [12], [13], [14], [15], [16], [22], but the draw backs are complexity and large area requirement on board. Lack of efficient implementation of ACS is a bottleneck for speed and area optimization of the architecture. Various convolution encoders of different code rate and constraint lengths are used in various types of data-communication channels. A single decoder at the receiver side which can be tuned for any channel would be a revolutionary step to save the resources. In [5] Viterbi decoding was limited to low data rates of 20 Mbps. A flexible Viterbi decoder [6] with data rate up to 70 Mbps was also proposed recently. In this paper, based on the Viterbi algorithm presented in [5] the core design is followed and implementation of the proposed structure uses an improved modular implementation of Add Compare Select (ACS) and Trace back units to obtain high speed [4]. Reconfigurable Viterbi decoder with a constraint length of 3–7, and a code rate of 1/2–1/3 using the Xilinx VirtexII-XC2Vp30 FPGA is presented in this paper.
The most popular representative devices of reconfigurable computing are field-programmable gate arrays (FPGAs). A promising feature of an FPGA is the ability to reuse the same hardware for different tasks at different phases of an application execution [19], [21]. Moreover, the tasks can be swapped on the fly while part of the hardware continues to operate. This is known as dynamic reconfiguration, and evaluation of its performance presents interesting research challenges [21]. Partial reconfiguration addresses the reduced reconfiguration overhead, coefficient flexibility and area efficiency for higher order Viterbi decoders [5], [18]. The objective of this work is to focus on the application of dynamic partial reconfiguration, to reduce reconfiguration overhead, code rate and constraint length flexibility and to improve area efficiency for Viterbi decoders.
This paper is organized as follows. Section 2 presents the design and implementation results for the multiplexer based reconfigurable VD. Section 3 presents the design method and implementation results for the dynamic partial reconfigurable VD. Section 4 presents the results for static reconfiguration VD and for multiplexer based reconfigurable VD design. Comparison of the different implementation methods are discussed in Section 5. Concluding remarks are given in Section 6.
Section snippets
Proposed architecture for reconfigurable Viterbi decoder
In the proposed architecture the functionality of Viterbi decoder has been realized by five modules named as Core_array, MIN_STATE unit (Minimum State Finder), Decision Memory, Reconstructor and LIFO as shown in Fig. 1. In the conventional architecture of Viterbi decoder the critical path delay was equal to sum of delay of ACS unit and the delay of Trace back unit. This delay is due to the time delay involved in finding the two possible state metrics (path metrics) for every state
Partial reconfigurable Viterbi design
Architecture shown in Fig. 9 is a partial reconfigurable architecture for code rate as well as constraint length. The core_array is the reconfigurable block in this architecture. It consists of 2 cores (CA1), 8 cores (CA2), and 32 cores (CA3) for constraint lengths 3, 5 and 7 respectively. So we can have three reconfigurable modules RM1, RM2, RM3 having bit streams of 2, 8 and 32 cores respectively. By using partial reconfiguration we can reconfigure only the necessary blocks to achieve
Implementation results of static and multiplexor based reconfigurable Viterbi decoder
To prove the efficacy of the DPR method, static reconfiguration of different constraint length Viterbi decoder was implemented and tested on Xilinx platform. Static reconfiguration means to configure the device completely before the system execution. If a new static reconfiguration is required, it is necessary to stop the system execution and then reconfigure the device it over again. Table 9 shows the device utilization for the conventional static reconfiguration method on Xilinx Virtex II Pro
Discussion
The reconfiguration time taken by constraint length K = 3, K = 5 and K = 7 dynamic partial Viterbi decoder modules on Xilinx PlanAhead platform for Implementation I of the proposed architecture is listed out in Table 7. To implement K = 3 Viterbi decoder, it requires 0.0295 ms using ICAP and about 0.3574 ms using JTAG. The measured reconfiguration time for K = 5 reconfigurable Viterbi decoder about 0.1164 ms using ICAP and 1.4118 ms for JTAG. To implement K = 7 Viterbi decoder, it is 0.4641 ms using ICAP and
Conclusions
This paper presents a novel reconfigurable Viterbi decoder architecture, which meets the high speed and low power requirements of most popular wireless standards, without using any parallel processing and pipelining. The proposed architecture is an efficient convolution decoder for constraint lengths 3–7 with code-rate 1/2 and 1/3 specifically for 802.11a wireless local area network, 3G cellular code division multiple access environments, UMTS and EDGE. The proposed architecture fulfils the
C. Vennila received her B.E. degree in Electronics and communication engineering from P.S.N.A College of Engg and Technology, India in 1992. She received the M.E. degree in VLSI systems from NIT, Tiruchirappalli. India, in 2002.She is currently pursuing her Ph.D. degree at NIT, Trichy. Her current research interests include Reconfigurable computing for wireless applications, Algorithms and Techniques for Cognitive Radio.
References (22)
- et al.
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
Integr, VLSI J
(2008) Error bounds for convolutional coding and an asymptotically optimum decoding algorithm
IEEE Trans Inform Theory
(1967)- et al.
A two-stage Radix-4 Viterbi decoder for multiband OFDM UWB system
ETRI J
(2008) - Nandula S, Rao Y, Embanath S. High speed area efficient configurable Viterbi decoder for WiFi and WiMAX systems. In:...
- Vennila Arasu C, Patel Alok Kumar, Upadhyay Jaimil, Lakshminarayanan G, Ko S. High speed reconfigurable Viterbi decoder...
- Chadha K, Cavallaro J. A reconfigurable Viterbi decoder architecture. In: Asilomor conference on signals, systems and...
- Campos J, Cumplido R. A runtime reconfigurable architecture for Viterbi decoding. In: International conference on...
- Cavallaro J, Vaya M. VITURBO: a reconfigurable architecture for Viterbi and Turbo decoding. In: IEEE international...
- Swaminathan S, Tessier R, Goeckel D, Burleson W. A dynamically reconfigurable adaptive Viterbi decoder. In: ACM/SIGDA...
- Rasheed R, Menoumi A, Pacalet R. Reconfigurable Viterbi decoder for Mobile Platform. In: IFIP international conference...
Cited by (8)
Design and implementation of high throughput FPGA-based DVB-T system
2016, Computers and Electrical EngineeringCitation Excerpt :Therefore, in this paper trace-back algorithm has been used for further implementation. After determining the trace-back path, specified values are stored in memory and passed to output through FILO (First Input Last Output) block [23–24]. Inner interleaving contains a bit-wise interleaving stage which is accompanied by a symbol interleaving and demultiplexer blocks.
High performance ACS for Viterbi decoder using pipeline T-Algorithm
2015, Alexandria Engineering JournalCitation Excerpt :At the same time the proposed architecture maintains its throughput compared to [18,19] and 44.25% higher than the reported [20]. In order to obtain more realistic results, Table 7 compares the proposed reconfigurable decoder which supports the coding rate 1/2, 2/3 and 3/4 with constraint length 7 with the reported architecture presented in [19–24]. When compared to the most recent one [19], the proposed architecture consumes 40.86% lesser area and almost maintains the same throughput.
A foreknowledge perception method of multi-stages machining accuracy in aviation turbine shafts based on hidden Markov model and Neural networks
2022, IEEE/ASME International Conference on Advanced Intelligent Mechatronics, AIMSleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability
2021, Analog Integrated Circuits and Signal ProcessingPower efficient low latency architecture for decoder: Breaking the ACS bottleneck
2019, International Journal of Circuit Theory and Applications
C. Vennila received her B.E. degree in Electronics and communication engineering from P.S.N.A College of Engg and Technology, India in 1992. She received the M.E. degree in VLSI systems from NIT, Tiruchirappalli. India, in 2002.She is currently pursuing her Ph.D. degree at NIT, Trichy. Her current research interests include Reconfigurable computing for wireless applications, Algorithms and Techniques for Cognitive Radio.
Alok Kumar Patel received his B.E. degree from K.N. Modi Institute of Engineering and Technology, Ghaziabad, Uttarpradesh, India in 2008 and M.E degree from NIT, Tiruchirappalli, India, in 2011. Currently he is working with Broadcom, India, as staff 1IC design.
G. Lakshminarayanan received the M.E. and Ph.D. degrees in electronics and communication engineering from Bharathidasan University, Tiruchirappalli, India, in 1995 and 2005, respectively. He is currently working as an Associate Professor in the Department of ECE, NIT, Tiruchirappalli. His current research interests include Reconfigurable Systems, VLSI based Wireless System Design, Algorithms and Techniques for Cognitive Radio and Network on Chip.
Seok-Bum Ko received his Ph.D. in Electrical & Computer engineering at the URI, USA in 2002. He is currently an associate professor in the department of Electrical & Computer engineering at the University of Saskatchewan, Canada. His research interests include efficient hardware implementation of computer system, computer arithmetic, digital design automation, and computer architecture. He is a senior member of IEEE computer society.
- ☆
Reviews processed and approved for publication by Editor-in-Chief Dr. Manu Malek.