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Computers & Electrical Engineering
Volume 33, Issues 5-6, September-November 2007, Pages 324-332
Security of Computers & Networks
 
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doi:10.1016/j.compeleceng.2007.05.005    How to Cite or Link Using DOI (Opens New Window)
Copyright © 2007 Elsevier Ltd All rights reserved.

HW/SW co-design for public-key cryptosystems on the 8051 micro-controller

K. SakiyamaCorresponding Author Contact Information, a, E-mail The Corresponding Author, L. Batinaa, B. Preneela and I. Verbauwhedea

aKatholieke Universiteit Leuven, Department Electrical Engineering – ESAT/SCD-COSIC Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium

Available online 29 June 2007.

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Abstract

It is a challenge to implement large word length public-key algorithms on embedded systems. Examples are smartcards, RF-ID tags and mobile terminals. This paper presents a HW/SW co-design solution for RSA and Elliptic Curve Cryptography (ECC) over GF(p) on a 12 MHz 8-bit 8051 micro-controller. The hardware coprocessor has a Modular Arithmetic Logic Unit (MALU) of which the digit size (d) is variable. It can be adapted to the speed and bandwidth of the micro-controller to which it is connected. The HW/SW co-design space exploration is based on the GEZEL system-level design environment. It allows the designer to find the best performance-area combination for the digit size. As a case study of an FPGA prototyping, 160-bit ECC over GF(p) (ECC-160p) was implemented on Xilinx Virtex-II PRO (XC2VP30). The results show that one point multiplication takes only 130 ms including all communications between the 8051 and the coprocessor. The performance is 40 times faster than the most optimized SW implementation on a small CPU in literature. This is achieved by the HW/SW co-design exploration in order to find the optimized digit size of the MALU. On the other hand, the design of ECC-160p maintains a high level of flexibility by using coprocessor instructions. Our proposed architecture proves that HW/SW co-design provides a high performance close to ASIC solutions with a flexible feature of SW even on a small CPU.

Keywords: HW/SW co-design; RSA; ECC; FPGA implementation; GF(p) operations; GEZEL

Article Outline

1. Introduction
2. Related work
3. Coprocessor architecture
3.1. Modular arithmetic logic unit (MALU)
3.2. Coprocessor memory
3.3. Finite state machine (FSM)
4. Software implementation on the 8051
4.1. Point multiplication
4.2. Point addition/doubling
5. System-level design and simulation
5.1. GEZEL system design environment
5.2. Instruction sets for coprocessor
5.3. Cost/performance estimation using GEZEL
6. FPGA implementation results of ECC-160p
7. Conclusions
Acknowledgements
References
Vitae






Computers & Electrical Engineering
Volume 33, Issues 5-6, September-November 2007, Pages 324-332
Security of Computers & Networks
 
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