Abstract

Property specification languages and ABV (assertion-based verification) driven by simulation are being recognized by many as essential for verification of today’s increasingly complex designs. In addition, there are few mature approaches that concentrate on improving assertion integration with high-level designs modeled in SystemC. This paper discusses the issues faced within SystemC environments to incorporate PSL (property specification language) assertions. It also proposes an automatic solution that enhances SOC (system on chip) SLD (system level design) flow with PSL assertions embedded into SystemC designs.

Keywords: ABV; SLD; PSL; BCA; SystemC; TLM

Article Outline

1. Introduction

2. Related work: assertion-based verification (ABV)

2.1. ABV approaches in RTL designs

2.2. ABV approaches in SystemC designs

3. SLD issues for extension using PSL

3.1. SLD flow definition

3.2. Advantages and limitations

3.3. Difficulties towards SLD flow extensions

4. Enabling PSL assertions in SystemC according to the proposed ABV approach

5. Application

5.1. Description of SOCs-based ST bus

5.2. Verification completeness estimation

5.3. ABV impacts on simulation speed

6. Conclusion and perspectives

Acknowledgements

References

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