doi:10.1016/j.aeue.2006.05.009 
Copyright © 2006 Elsevier GmbH All rights reserved.
A new low voltage CMOS differential OTRA for sub-micron technologies
aSTMicroelectronics, Buyukdere Cad. ITU Ayazaga Kampusu, ARI 2 Teknokent B Blok No:3-1, 34469 Maslak, Istanbul, Turkey
bFaculty of Electrical and Electronics Engineering, Department of Electronics and Communication Engineering, Istanbul Technical University, 34469, Maslak, Istanbul, Turkey
Received 2 February 2006.
Available online 18 July 2006.
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Abstract
In this study, a new CMOS differential operational transresistance amplifier (OTRA) topology is proposed. This topology can operate with a very low voltage power supply as 1.2 V. In this design, CMOS 
STMicroelectronics technology transistor models are used for the simulations. The designed CMOS OTRA has a transresistance gain (Rm) of 38 660 V/A with a bandwidth 
of 29.2 MHz. To demonstrate the performance of the OTRA, designed universal MOS-C filter employing two CMOS differential OTRA are tested with CADENCE simulation program to verify the theoretical results.
Keywords: OTRA; Low voltage; Sub-micron; Universal filter
Fig. 1. Circuit symbol of the differential OTRA.
Fig. 2. Proposed differential CMOS OTRA topology.
Fig. 3. Basic cell of the OTRA input stage.
Fig. 4. Basic cell of the OTRA gain stage.
Fig. 5. Opamp used in the OTRA as a unity gain output buffer.
Fig. 6. Typical dc simulation result of OTRA.
Fig. 7. Typical dc simulation result of OTRA with different I2 input currents between -2 and 2 mA with 
steps.
Fig. 8. Typical ac simulation result, normalized transresistance gain of the OTRA.
Fig. 9. MOS structure (V2→0).
Fig. 10. Universal MOS-C filter topology with CMOS OTRA.
Fig. 11. Universal MOS-C OTRA filter frequency response (BP, HP, LP, Notch, AP).
Fig. 12. The phase response of the universal MOS-C OTRA filter in Allpass (AP) mode.
Fig. 13. Dependence of the output harmonic distortion of Lowpass filter on input voltage amplitude with 1 MHz signal.
Table 1.
Transistor dimensions (W/L) in the proposed CMOS differential OTRA
Table 2.
Transistor dimensions (W/L) and other devices values in the proposed OPAMP
Table 3.
Performance of the proposed CMOS differential OTRA
Table 4.
The simulated cut-off frequency 
error percentages for all the filter types
Abstract
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