Optimised sparse storage mode for symbolic analysis of large networks

https://doi.org/10.1016/j.advengsoft.2006.07.002Get rights and content

Abstract

Symbolic network analysis gained growing interest as it aims at producing outputs in the form of expressions that containing both variables and numbers. However, such analysis faces the primary difficulty of the exponential growth of product terms in a symbolic network function with respect to circuit size. This long-standing difficulty is only partially overcome by various symbolic approximations and hierarchical decomposition approaches. A new storage scheme called Row-Indexed Semi-Symmetric Sparse (RISS) storage mode that partially solves this difficulty is presented in this paper. Unlike other similar storage schemes, the proposed scheme requires only about twice the number of nonzero matrix elements at most. The efficiency of the proposed RISS storage mode is assessed by considering several matrices of moderate sizes and comparing the memory requirement for each matrix in full storage mode and in RISS storage mode. The overall performance of a solver that incorporates the RISS storage mode and the sparse matrix techniques is assessed by considering a typical example of a 90° phase splitting network. When compared to an alternative matrix solver based on successive matrix reduction, the proposed solver demonstrates a reduction of 65% in the operation count and a reduction of 60% in the average memory storage requirement.

Introduction

Symbolic analysis is a complement to numerical simulation in the design and evaluation of integrated circuits. It provides insight into circuit behaviour that numerical analysis does not. It calculates the behaviour or characteristics of a circuit with the independent variable (time or frequency), the dependent variables (voltages and currents), and some (or all) of the circuit elements being represented by symbols [1]. Despite the rapid development of several symbolic-analysis tools for analogue and digital circuits in the past several years [1], [2], [3], the circuit sizes that can be handled by such tools are still much smaller than those handled by numerical simulators. The main difficulty is the exponential growth of product terms in a symbolic network function with respect to the circuit size. This long-standing difficulty can only be partially overcome by various approximation and hierarchical decomposition approaches [4], [5].

Symbolic approximation can be performed before, during or after the generation of symbolic terms [2], [5]. The approximated expressions however only have sufficient accuracy over some frequency ranges. Moreover, approximation often loses some information that is crucial for circuit optimisation. Hierarchical decomposition approaches are based on the sequence-of-expressions concept to obtain the network transfer function [6], [7], [8]. The decomposition process initially eliminates variables one at a time in each sub-circuit. The obtained results from sub-circuits analyses are then combined to form the upper-level circuit equations. In this approach, the transfer function is trivially computed from the resulting equations and the intermediate results are not compact enough. The number of expressions is therefore grows rapidly with respect to the circuit size and consequently the CPU operation count and memory storage requirement increase too. A graph-based hierarchical method for the generation of exact symbolic network functions is reported in [3], [6], [7]. This method is a direct implementation of the Laplace expansion and it has the same time complexity. It employs a determinant decision diagram that is a signed rooted directed acyclic graph with two terminal vertices. The algorithm needed to automate this process can therefore be combined with sparse matrix algorithms to find the determinant. However, for a heavily connected network the efficiency of this method is reduced since the operation count increases rapidly as the number of nonzero symbolic coefficients increases.

Consideration of matrix sparsity is quite important in the implementation of most network analysis techniques. It often happens that the ability to ignore the number of equations completely changes the equation formulation procedure itself [9]. Because of its extensive requirements of computer resources, the symbolic matrix sparsity has not received large coverage in the literature in the past. However, the recent advances in computer technology and availability of more efficient algorithms offer great opportunities to develop symbolic analysis tools that are capable of handling much larger networks than ever before.

The symbolic solver considered in the present work was previously reported in Ref. [10]. This solver which integrates the analysis of both lumped and distributed networks returns symbolic formulae for any node voltage or branch current as well as transfer functions, noise, poles and zeros, etc. The entire structure of this solver is divided into four procedures. The main functions performed by each of these procedures are summarized in the simplified flowchart of Fig. 1. The work presented in this paper focuses on optimising the operation count and memory storage requirement of this solver using a new storage scheme called Row-Indexed Semi-Symmetric Sparse (RISS) storage mode. As this topic involves considerable “technique” rather than concept, the symbolic sparse routines are presented with a particular emphasis on their applications in symbolic circuit analysis.

Section snippets

Indexed storage of sparse matrices

The use of sparse matrix techniques results in a substantial reduction in computing cost even for relatively small problems. Unfortunately, however, sparse matrix software development is rather a difficult task and is completely application-dependent. Before delving in the details, the importance of such techniques is initially justified. It is well known that the number of operations necessary to solve a system of equations by Gaussian elimination or by LU factorisation is approximately n3/3.

The proposed RISS storage mode

A new storage scheme which is called Row-Indexed Semi-Symmetric Sparse (RISS) storage mode is described in this section. Unlike alternative storage schemes that may require as much as three to five times [11], the proposed scheme requires storage of only about twice the number of nonzero matrix elements at most. Taking into consideration that the symbolic entries of the matrix may take a huge memory size compared to the integers representing their indices, this method takes about the same

Overview of sparse matrix techniques

A network solver based on sparse matrix techniques performs either a matrix decomposition or elimination. The major difference from a conventional matrix solver is that the input, intermediate, and the resultant matrices are dealt with as sparse arrays (vectors) during the elimination or factorisation. In such process, however, the number of operations can be reduced substantially by the proper selection of the pivot. Choosing some permutation of rows and columns that minimizes the number of

Implementation of sparse solver

Practically, it is a rare case to have only one set of simultaneous equations to be solved in the computer analysis of a network. It is also very common that these equations retain the same structure during the solution, as it is the case in optimisation and circuit design. In this context, the factorisation, elimination, and forward/backward substitution processes for sparse matrices are examined to determine which operations need to be performed only once and which must be performed at each

Results and discussion

The efficiency of the proposed RISS storage mode is assessed by considering several matrices of moderate sizes and comparing the memory requirement for each matrix in full storage mode and in RISS storage mode. Fig. 3 shows comparison results between the storage requirement and the storage density. The storage requirement in this figure is represented as a percentage of the full-mode storage requirement that is averaged for many matrices. The matrix density is expressed as the ratio of nonzero

Conclusions

In this paper a new sparse storage scheme based on the special properties of circuit matrices has been described for symbolic matrices. The proposed scheme is optimised through an efficient implementation within a complete sparse solver. The performance of this solver is further enhanced through the incorporation of the code interpretation algorithm that generates machine op-code directly to evaluate the solution. The adopted interpretive code approach speeds up the solution, as the indexing

References (15)

  • G.E. Gielen et al.

    A symbolic simulator for analog integrated circuits

    IEEE Trans Solid-State Circuits

    (1989)
  • J.J. Hsu et al.

    DC small signal symbolic analysis of large analog integrated circuits

    IEEE Trans Circuits Systems-Fundamental Theory and Applications

    (1994)
  • C.-J. Shi et al.

    Canonical symbolic analysis of large analog circuits with determinant decision diagrams

    IEEE Trans Computer-Aided Design

    (2000)
  • F. Fernandez et al.

    Symbolic analysis techniques

    (1998)
  • Q. Yu et al.

    A unified approach to the approximate symbolic analysis of large analog integrated circuits

    IEEE Trans Circuits Syst

    (1996)
  • C.-J.R. Shi et al.

    Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design

    IEEE Trans Computer-Aided Design

    (2001)
  • X.-D. Tan et al.

    Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams

    IEEE Trans Computer-Aided Design

    (2000)
There are more references available in the full text version of this article.

Cited by (2)

View full text