Tabu search based circuit optimization

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Abstract

In this paper we address the problem of optimizing mixed CMOS/BiCMOS circuits. The problem, formulated as a constrained combinatorial optimization problem is addressed using a tabu search algorithm. Initially a random approach is adopted for selecting among available solutions. Further, as an alternative competing solution the concepts of simulated evolution are applied to classical tabu search (CTS). This allows for a stochastic criterion for selecting among available solutions as compared to the random approach of CTS. Only gates on the critical sensitizable paths are considered for optimization. Such a strategy leads to sizeable circuit speed improvement with minimum increase in the overall circuit capacitance. Compared to earlier approaches, the presented techniques produce circuits with remarkable increase in speed (greater than 20%) for very small increase in overall circuit capacitance (less than 3%).

Introduction

Popularity of CMOS technology is due to its low DC power dissipation and high package density. The demand for superior performance motivated research and development that lead to the emergence of BiCMOS technology. BiCMOS is a combination of CMOS and Bipolar technologies, with advantages of both, high speed and high driving capabilities of Bipolar, as well as the low area and low power consumption of CMOS.

VLSI designs are evaluated with respect to three main performance criteria: speed, area, and power consumption. As these criteria are conflicting designers usually seek to optimize one criteria, namely speed, while satisfying specific constraints/requirements on area and power consumption.

One of the optimization techniques applied at the circuit level is the selection of logic blocks of the VLSI circuit, in terms of speed and area. For example, for standard cell designs, the optimization can be performed through a careful selection of different implementations of a block in the same technology. These alternative implementations vary in area, driving capabilities, intrinsic delay, and capacitive loading (Lin et al., 1990). Another optimization strategy is to follow a mixed technology design approach. One possible choice is to mix CMOS/BiCMOS technologies. In terms of manufacturing process, this is feasible since the CMOS process is part of BiCMOS process. The CMOS-based BiCMOS process is a CMOS baseline process to which bipolar transistors are added. So, for a mixed design circuit, initially all cells are exposed to CMOS process. Then bipolar transistors are added to only those cells that are selected to be BiCMOS.

In this paper we discuss the problem of optimizing mixed CMOS/BiCMOS circuits in terms of delay, power and area. Although the scope of the work is directed to CMOS and BiCMOS technologies, other technologies can be included taking into consideration the feasibility and practicality of mixing these technologies.

The basic idea is as follows. Given a circuit consisting of only CMOS cells, some of those cells are selected and replaced by their equivalent BiCMOS cells in such a way that the entire delay of the circuit is decreased with a minimum increase in power and area.

In Baba-Ali and Bellaouar (1994), the above approach for optimizing standard cells circuits is used. The technique aims at improving circuit performance by making for each gate, a choice between CMOS or BiCMOS cells depending only on their load capacitance. The authors reported noticeable speed improvement on all the test circuits used. However, in their implementation, no constraints on power dissipation were placed, and the number of BiCMOS gates was high. The reported approach suffers from several problems, namely:

  • 1.

    All the nodes are considered for optimization.

  • 2.

    Output nodes are replaced whether they are on time critical paths or not.

  • 3.

    The approach is local; that is, it performs the optimization on a single node. It does not have a global view of the circuit; hence it is expected to get trapped at a local optimum solution.

The actual delay of a circuit is determined by the delay of its longest sensitizable path. A sensitizable path is a path which can be activated by at least one input vector. Those paths which cannot be activated by any input vector are called false paths. A path is critical if its total delay is greater than a threshold value. Thus, the problem of finding and estimating the delay of critical paths is called the critical path problem (Chen et al., 1993). For static timing analysis techniques, the circuit is modeled as a directed acyclic graph in which three popular algorithms are used to trace the paths: depth first search (DFS) with/without pruning, breadth first search (BFS), and PERT-like trace.

In this work we enumerate all sensitizable critical paths according to the α-critical concept. First, all paths with average delay (including estimation of interconnect delays) exceeding an estimated threshold value are enumerated. From amongst these paths, only sensitizable paths are reported.

In the following section we discuss the α-critical approach. Discussion on false path problem is given in Section 3. The circuit optimization problem (COP) is formulated as a combinatorial optimization problem in Section 4. Details of application using tabu search (TS) are given in Section 5. Use of some simulated evolution (SE) concepts with TS for the COP are presented in Section 6. Experimental results are provided in Section 7.

Section snippets

The α-critical approach

The delay of the circuit is determined by its longest sensitizable paths. Therefore, to verify and optimize the circuit timing, the focus should be on predicting the timing critical paths only. A path π is classified as critical if its total delay, Tπ, is very close to its latest required arrival time LRATπ. If Tπ exceeds LRATπ, path π becomes a long path. The path delay consists of two components: the logic delay which is known prior to layout, and the interconnect delay which is unknown. In

False path problem

The presence of false paths has many undesirable effects which include loss of accuracy and waste of optimization effort. False paths exist in a circuit because of several reasons, namely:

  • 1.

    Incompatible transitions: A false path results from the combination of incompatible transitions.

  • 2.

    Incorrect signal flow: Timing verifiers that operate at switch level encounter this problem. Due to the bidirectional nature of MOS transistors, the intended signal flow in a structure such as the barrel shifter is

Optimization of BiCMOS/CMOS VLSI designs

The problem of optimizing a mixed technology design can be formulated as an optimization problem and solved using a variety of algorithms. For a mixed CMOS/BiCMOS design, there exist 2m solutions for a circuit with m gates. Hence, full/brute force design space exploration is infeasible even for designs of moderate sizes.

TS algorithm

Tabu search is an iterative procedure that works by making moves from one trial solution to another. An algorithmic description of a simple implementation of TS is given in Fig. 2.

The TS procedure starts from an initial feasible solution s (current solution) in the search space Ω. A neighborhood ℵ(s) is defined for each s. A sample of neighbor solutions V∗⊂ℵ(s) is generated called trial solutions (n=|V∗|⪡|ℵ(s)|), and comprises what is known as the candidate list. From this generated set of

Evolutionary tabu search

As mentioned in the previous section moves can be generated by selecting gates based on their attributes. This approach is based on the evolutionary aspects of the SE heuristic. Before explaining how this can be done, an overview of SE is presented.

Results and discussion

The approach described in this paper has been tested on several ISCAS-85 benchmark circuits. For the nine ISCAS-85 circuits used, the percentage of false paths reported ranged from 0 to 24%. Note that these are false paths from among the critical paths. In all but one case the maximum delay of the circuit did not change due to removal of false paths, but the number of gates on the sensitizable paths was reduced. For Classical TS, experiments with short term and long term components were

Acknowledgements

The authors acknowledge the King Fahd University of Petroleum and Minerals, Dhahran, for support. Also, the assistance rendered by Mohammad Faheemuddin is appreciated.

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