Numerical errors of the real time dynamic correction for the current measurement

https://doi.org/10.1016/S0920-5489(99)00014-8Get rights and content

Abstract

The finite precision of arithmetic operations performed by a processor is the source of numerical errors. An algorithm of the dynamic error correction has been tested with respect to the numerical errors. A truncation operation of any bit number representation has been simulated. A floating-point and fixed-point processors have been tested during simulations. Two criteria ‖ ‖2 and ‖ ‖ have been examined.

Introduction

A current response of an inverter fed drive is a non-sinusoidal shape. Moreover, the output signal of the current sensor (low inductance shunt Rsh) is much lower in comparison to the span of the input range of the A/D converter. Therefore, this signal has to be amplified. The amplifier is usually described as the first order object of gain k and time constant Ta:Ga(s)=k1+sTa,where Ta=(2πfa)−1, fa — amplifier bandwidth (−3 dB).

The higher the gain yields the higher the time constant of the amplifier. This is the source of considerable dynamic errors of the current measurement. An algorithm performed by a digital signal processor might be used for correction of this error in real time. The simple Gear algorithms of the first (Eq. (2)) and the second (Eq. (3)) order have been suggested for this task.

Simulation results of the instantaneous current value reconstruction were presented during MMAR'97 [1]. The influence of the sampling period TS, amplifier time constant Ta and electromagnetic time constant TO to the accuracy of this correction have been examined. These algorithms appeared to be useful and efficient.

A 12-bit A/D converter of 10 V input span has been used as a standard device for the digital measurement. It is sufficiently precise and fast enough. A sampling frequency fS=100 kHz has been assumed (sampling period TS=10 μs). The question is: what bit number processor should be used with respect to the precision of correction?

The presented paper concerns the numerical errors generated by a reduced bit number p of the processor word. The cheaper processors use shorter words. Additionally, most processors use the fixed-point arithmetic instead of floating-point. During the simulation the processors of 16-, 24- and 32-bit word have been taken under consideration. The examined algorithm is not complicated thus a simple processor can perform it. FPGA structures (e.g., XILINX family 4000 [2]) might be organised to perform this algorithm as well. Therefore, the bit number may be freely chosen (e.g., 12-, 20-, 28-bit). Any number or variable during simulation has been converted to the format that corresponds to the physical representation of it in processor registers. For that reason the errors caused by the number truncation ought to be examined.

Section snippets

Algorithm of the dynamic error correction

The Gear algorithms of the first and second order for differential equations have been applied. , describe the method of the amplifier input signal reconstruction.îI(n)=(TG+TS)uD(n)−TGuD(n−1)kRshTs for n=1,…,N;îII(n)=(3TG+2TS)uD(n)−TG(4uD(n−1)+uD(n−2))2kRshTs for n=2,…,N.where TS is the sampling period, TG the estimated value of the time constant Ta, uD(n) the result of the A/D conversion for time nTS, îI(n) the recovered value of the current for time nTS (the 1st order algorithm), and îII(n)

Number representations

The IEEE standard for binary floating-point arithmetic has been used for DSP [3]. The number representation has the following form:X=(−1)S2E(b0b1b2…bp−1),where S is the sign bit, that denotes the sign of the number: S=0 for X>0, S=1 for X<0, E the exponent of the floating-point number, and bi the bits of the fractional field of the number representation (i=0, 1, …, p−1).

Every number has been converted to this format during simulation. The less significant bits of the fractional field have been

Criteria

A difference between emulated instantaneous measurement value corrected by a p-bit word processor and a value calculated in the double precision format has been treated as a numerical error. The errors have been referred to the 12-bit A/D resolution and presented in LSB value of this converter. The two standard criteria such as: maximum absolute value of the dynamic error Qmax as ‖ ‖ and sum of the squares of the errors Q2 as ‖ ‖2, over the fixed time period of simulation have been examined.

Simulation results

A period 1 ms of inverter commutation has been simulated. The correction algorithms of the first and the second order have been tested for the fixed- and floating-point arithmetic and a chosen number bits p of the number representation. At moment t=0 the voltage UDC=+600 V has been switched on to the drive of electromagnetic time constant TO=10 ms and resistance R=7 Ω. The shunt of the resistance Rsh=0.05 Ω converts the drive current to the voltage. The amplifier of the gain k=25 and time

Conclusions

As a result of this simulation it has been turned out that processors with the fixed-point arithmetic deal quite well with the applied algorithms. There is no necessity to use floating-point processors.

For the wide range of the amplifier time constant the 16-bit representation of the number is sufficient. Errors caused by the truncation of the number representation are not higher than 1 LSB.

If the sampling period is not shorter than 1 μs, a simple and cheap processor with 30 MHz clock can

Acknowledgements

The study was financed from KBN grant No. 8T10C00513.

Jerzy Nabielec was born in Cracow, Poland, on March 28, 1954. He received the MSc, PhD degrees from University of Mining and Metallurgy in Cracow, Faculty of Electrical Engineering, Automatics and Electronics, in 1978 and 1989, respectively. Now he is working as academic lecturer at University of Mining and Metallurgy, Department of Instrumentation and Measurement. His research interest includes modelling and simulations of measuring systems and their elements, dynamic error correction, real

References (3)

  • Morończyk, J. Nabielec, DSP dynamics error correction of the current measurement for electrical drives, in: Proc. of...
There are more references available in the full text version of this article.

Cited by (0)

  1. Download : Download full-size image
Jerzy Nabielec was born in Cracow, Poland, on March 28, 1954. He received the MSc, PhD degrees from University of Mining and Metallurgy in Cracow, Faculty of Electrical Engineering, Automatics and Electronics, in 1978 and 1989, respectively. Now he is working as academic lecturer at University of Mining and Metallurgy, Department of Instrumentation and Measurement. His research interest includes modelling and simulations of measuring systems and their elements, dynamic error correction, real time algorithms, DSP, analysis of the influence of measuring equipment parameters on measurement errors. He has published 32 conference and journal papers in this field.
  1. Download : Download full-size image
Adam Morończyk was born in Czechowice-Dziedzice, Poland, on October 13, 1969. He received the MSc degree from University of Mining and Metallurgy in Cracow, Faculty of Electrical Engineering, Automatics and Electronics, in 1994. Now he is working as academic lecturer at University of Mining and Metallurgy, Department of Instrumentation and Measurement. His research interest includes testing algorithms implemented at DSP, dynamic error correction and measurement of the non-sinusoidal signals (parameters like: RMS, THD, active and reactive power). He has published 15 conference and journal papers in this field.

1

Tel.: +48-12-617-3299; fax: +48-12-633-8565; e-mail: [email protected].

View full text