Upper yield point of large diameter silicon

doi:10.1016/S0167-9317(00)00512-8

Microelectronic Engineering

Volume 56, Issues 1–2, May 2001, Pages 117-122

https://doi.org/10.1016/S0167-9317(00)00512-8 Get rights and content

Abstract

The temperature and shear strain rate dependence of the upper yield point of a few kinds of large diameter silicon crystals was studied. Crucial material attributes, such as doping level, initial oxygen content, and the state of oxygen aggregation after thermal treatment, were taken into account. Overall experimental results show that the deformation behavior of the materials studied here is similar; there is no difference observed between high and low boron-doped 200-mm-diameter and 300-mm-diameter silicon crystals. Further, the right choice of sample orientation and shear strain rate used in experiments have been proved to be significant for the characterization of mechanical strength of silicon wafers subjected to process load. Very low strain rates and forces lying in crystallographic 〈110〉 directions generate local regions of plastic flow caused by an extremely low yield stress. The results allow the optimization of critical high temperature processes used for materials technology and device fabrication.

Introduction

Under gravitational and thermal constraints of integrated-circuit process technology, 300-mm-diameter silicon wafers can deform via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. Thus, slip-free high temperature processing of 300-mm wafers is currently a primary engineering challenge in bringing large wafer utilization to a production-level maturity [1]. The procedure to determine the process conditions, which prevent plastic deformation, involves relating the effect of gravitational and transient thermal constraints to the mechanical strength of the wafers [2]. At elevated temperatures, an important physical measure of the crystal strength and deformation resistance of elemental and compound semiconductors is the upper yield stress determining the onset of plastic flow under load. The yield behavior is also of practical interest for the susceptibility of the seed during crystal growth.

There is only a limited number of stress–strain investigations on Si, with main emphasis on the single slip orientation in the stereographic triangle and performed on crystals under very high strain rates [3], [4], [5], [6], [7]. It will be shown in Section 2 that both conditions are nonrelevant for the study of the deformation onset of wafers subjected to mechanical and transient thermal loads arising in process technology. Detailed experimental results of τ_uy, for typical concentrations of dissolved and precipitated oxygen atoms in large wafer material have also not been available. Our purpose here is to provide key data for the temperature and strain rate dependence of upper yield stress for a few types of 200-mm-diameter and 300-mm-diameter silicon crystals of preferred orientation and characteristical oxygen content. Over a wide temperature range, we show how the magnitude of temperature dependence (Arrhenius factor) of the yield point diminishes as the strain rate decreases. The semi-empirical analysis used shed light on some remarkable practical results.

Section snippets

Stress–strain experiments

The upper yield stress of a covalently bonded crystal such as silicon decreases with increasing temperature, dislocation densities, precipitated oxygen content, and with slower strain rates. Further, the stress values required for plastic flow drop when the number of simultaneously activated slip systems is reduced, with the exception of the single slip orientation in the stereographic triangle. On stressed (001) Si wafers, stresses in 〈110〉 directions with a high Schmid factor of $1/6$ activate

Temperature and strain rate dependence of the upper yield point

As indicated in the previous section, we studied a few material kinds of large Si wafer diameters. Crucial material attributes, such as dislocation content, doping level, initial oxygen concentration, and amount of average oxygen precipitation after thermal treatment, were taken into account. Overall experimental results show that the deformation behavior of the material kinds studied here is similar; there is no difference observed between high and low p-doped or 200-mm-diameter and

Summary and conclusions

We studied the thermo-mechanical strength of a few types of 200-mm-diameter and 300-mm-diameter silicon crystals with characteristic oxygen content. To find experimentally the minimum upper yield stress on the wafer, a specific orientation of specimens and very low strain rates were chosen. The results obtained are sufficient to quantitatively determine the high temperature processing windows in integrated-circuit fabrication. As a data set for the yield point of 200/300-mm-diameter silicon

Acknowledgments

This work was supported by the Federal Department of Education and Research of Germany under contract No. 01 M 2973 A. The authors alone are responsible for the content. The authors would like to thank Professor A. Ourmazd and Dr. J.A. Moreland for critical reading of the manuscript.

References (10)

A. Fischer et al.
Microelectr. Eng.
(1999)
S. Mahajan et al.
Acta Metall.
(1979)
H.R. Huff et al.
J.R. Patel et al.
J. Appl. Phys.
(1963)
G. Bentini et al.
J. Appl. Phys.
(1984)

There are more references available in the full text version of this article.

Cited by (20)

Damage threshold of substrates for nanoparticles removal using a laser-induced plasma shockwave
2021, Applied Surface Science
Citation Excerpt :
The literature indicated that the yield strength value could be used to determine whether a substrate was damaged and varied with temperature. Overall, the yield strength decreases sharply with increasing temperature [23,24]. As shown in Table 2, at a temperature of approximately 1000 K, the yield strength of the silicon material sharply decreases to 61 MPa.
With technological advancement, plasma shockwaves have become widely used as a novel cleaning method to remove nanoparticles. However, insufficient research has been conducted on their cleaning mechanism and application conditions, and the yield strength of substrates has been directly used as their damage threshold. we find that this definition is inaccurate. We treat clean and nanoparticle-coated silicon substrates with a laser-induced plasma shockwave to explore the effects of the presence of nanoparticles on the substrate during cleaning. We have confirmed the effect of nanoparticles on the substrate by simulating the mechanism of temperature and stress propagation between the particles and the substrate. This is because the yield strength of the substrate is greatly reduced by the increase of temperature under the action of shock wave. At the same time, the stress transferred by particles to the substrate increases, resulting in local high-pressure area and pit formation. Moreover, this study finds that the presence of nanoparticles increases the probability of damage to the substrate by an approximate factor of two. And the dependence of the damage threshold of the substrate on the size of the nanoparticles is demonstrated.
Simulation of plastic deformation of sculptured diaphragm silicon microstructure
2016, Microelectronic Engineering
Citation Excerpt :
Research on plastic deformation of silicon was first reported in 1952 [12]. Most of previous researches are concentrated on material characteristic, such as dislocation and slip in silicon [13,14,15,16,17], stress–strain characteristics in yield deformation of Si [18,19], yield stress [20,21], and effects on silicon material properties [22,23,24,25]. Although the plastic deformation and strain can be calculated using the plastic material model in finite element simulation directly, the plastic model parameters of silicon like yield function, hardening rule and temperature dependent properties are still inadequate especially when the temperature is up to 1100 °C.
Single crystal silicon MEMS microstructures could be plastically deformed during high-temperature manufacturing process. In this paper, an iterative finite element simulation method based on Von Mises yield criterion is proposed to determine the plastic deformation of silicon microstructure. In the proposed method, the critical condition for plastic deformation is that the maximum Von Mises stress of the microstructure equals to the yield stress. Sculptured diaphragm microstructures with different dimensions are designed to verify the method. Plastic deformation of the structure is measured after the annealing process of 1100 °C. The simulation value fits the experiment well and the average deviation between the simulation data and experimental data is 2.2%.
Plastic deformation in 200 mm silicon wafers arising from mechanical loads in vertical-type and horizontal-type furnaces
2009, Materials Science and Engineering: B
Slip-free high temperature processing of silicon wafers at temperatures up to 1200 °C still remains an engineering challenge. Therefore, the authors present the physical basis for estimation of gravitational constraints in 200 mm silicon wafers subjected to high temperature processes both in vertical-type and horizontal-type furnaces. The load-induced shear stresses in 200 mm silicon wafers stacked horizontally and vertically were calculated using 3D-FEM analysis of the displacement vector assuming linear elastic behavior of the anisotropic material. For comparison of the two complex loading cases and for relating the effect of gravitational constraints to the mechanical strength of the wafers, the invariant Von Mises shear stress was chosen. Calculation of load-induced stresses and determination of the onset of plastic deformation have shown that for vertical-type boats annealing at temperature >850 °C would lead to slip formation in the bearing area of the wafer whereas for horizontal-type boats largely slip-free processing would be possible up to 1200 °C.
Process-induced transfer pattern in Si epitaxy using pocket susceptor
2005, Journal of Crystal Growth
The vapor-phase epitaxial growth of silicon epwafers using pocket susceptor is studied. Characteristic transfer patterns are frequently observed on the backside wafer surface. The pattern has the shape of tree-rings extending from the wafer edge. The size and shape of the transfer pattern is sensitive to the growth sequence and the process condition such as growth temperature. The pattern is attributed to the chemical transfer of the coating from the pocket to the sagging front of the wafer. It is discovered that the tree-ring pattern is a true record of the process history. Each ring can be assigned to a particular growth step and vise versa. A close examination of the ring pattern provides valuable insight on wafer sagging in response to the process change. The result of pattern transfer is compared with that using a flat susceptor.
Empirical inference of in situ wafer sagging in Si epitaxy using pocket susceptor
2005, Journal of Crystal Growth
An empirical description of wafer sagging during silicon epitaxy using a dish-shaped susceptor pocket is presented. The proposed method is based on the discovery that the process history can be retrieved from the transfer pattern on the wafer backside. The characteristic tree-ring pattern is due to the contact transfer of the susceptor coating to the sagging wafer. Each ring is uniquely identified as a process step and vice versa. The number of rings is related to the growth schedule. The size and shape of the rings are sensitive to the growth conditions. A full picture of the in situ wafer sagging can be reconstructed by examining the transfer pattern after the wafer is unloaded from the reactor. The proposed method has been used to evaluate the wafer deformation in response to changes in the key process variable such as the growth temperature, susceptor geometry and reactor design.
Operating limits for RF power amplifiers at high junction temperatures
2004, Microelectronics Reliability
LDMOS RF––power amplifier components usually operate under severe conditions challenging long-term reliability. These components are subjected to high power dissipation and consequently high junction temperatures. Failure mechanisms are highly temperature dependent and driven by coupled electro-thermo-mechanical fields as a function of stress time. In this work we have investigated the reliability of such a component. Power cycling was used to assess its reliability by introduction of temperature gradients and transient at elevated junction temperatures. The experimental lifetime acceleration conditions provided transient thermal constraints to the thermo-mechanical strength of the silicon die. Power dissipation has been adjusted to cover a broad temperature range ( $T_{jmax}$ : 200–300 °C) in the peak of a single power cycle. Different failure modes have been observed and related to the different temperature ranges. The experimental results have been combined with thermo-mechanical FE-simulations in ANSYS, leading to the validation of simulation models and implementation in a larger simulation network. The power cycling approach as applied in this paper provided a useful addition to the steady state reliability information. In this way, clear information about margins for safe operation under dynamical conditions has been obtained. This information is needed to fully exploit the functional capability of the component and avoid over-specification in the final application. Overall, the LDMOS RF–PA component showed excellent reliability which makes it suitable for application in telecom devices.

View all citing articles on Scopus

View full text