doi:10.1016/S0167-9260(98)00021-2 
Copyright © 1998 Elsevier Science B.V. All rights reserved
BIST for systems-on-a-chip
Institute for Computer Science, University of Stuttgart, Breitwiesenstrasse 20-22, 70565 Stuttgart, Germany
Available online 23 March 1999.
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Abstract
An increasing part of microelectronic systems is implemented on the basis of predesigned and preverified modules, so-called cores, which are reused in many instances. Core-providers offer RISC-kernels, embedded memories, DSPs, and many other functions, and built-in self-test is the appropriate method for testing complex systems composed of different cores. In this paper, we overview BIST methods for different types of cores and present advanced BIST solutions. Special emphasis is put on deterministic BIST methods as they do not require any modifications of the core under test and help to protect intellectual property (IP).
Author Keywords: BIST; Systems-on-chip; Deterministic BIST; Functional BIST
Fig. 2. Test-per-scan scheme.
Fig. 3. Control signals of a test register.
Fig. 4. RT-example and test units.
Fig. 5. BIST control lines and their assignment.
Fig. 6. Standard linear feedback shift register (SLFSR).
Fig. 7. Testing and AND-gate.
Fig. 8. Modular linear feedback register.
Fig. 9. Signature analysis.
Fig. 10. Circular BIST, circular self-test path.
Fig. 11. Basic cell for circular BIST.
Fig. 12. Adding an LFSR to a circular self-test path.
Fig. 13. Clustering may destroy the BIST capability.
Fig. 14. Structure of a control unit.
Fig. 15. Controller structure obtained by conventional synthesis procedures (a) and required modifications for BIST (b).
Fig. 16. Example for utilizing the pattern generation capability of the state register.
Fig. 17. BIST structure with integrated pattern generator (PAT).
Fig. 18. Self-testable control unit by Agramal et al. [35].
Fig. 19. Parallel self-testable structure with integrated signature analysis (PST).
Fig. 20. Modified LFSR sequences.
Fig. 21. General form of bit-flipping BIST.
Fig. 22. BIST scheme based on multiple polynomial LFSR.
Fig. 23. A typical accumulator structure used as test pattern generator. In each cycle the constant content or register c is added to register r. The content of register r is a test pattern.
Table 1. Expected number E(m, s) of bits to be flipped
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